You might have an issue with the L1 cache.
The L1 cache sits between the CPU core and the memories, so all code and data accesses made by the program are going through the cache, but DMA accesses bypass this cache. The scenario might be something like this:
- DMA receive is started, incoming data is copied from the SPI receiver to memory.
- The program is busy doing things, the cache is occupied by all sorts of data.
- DMA flag is set, the program starts to examine the contents of the receive buffer.
- One line is evicted from the cache, and the buffer contents are read into this cache line. Because of (1.) you are lucky this time, the program has valid data to work on.
- The program starts to write data into the transmit buffer.
- Another cache line is evicted, and allocated for the write buffer.
- Because the default caching mode is write-back write-allocate, outgoing data is accumulated in the cache.
- The program finishes writing the transmit buffer, and starts the SPI DMA transmission.
- DMA reads the data from memory and copies it to the SPI data register.
- The program starts doing other stuff with another set of data.
- The contents of the transmit buffer are eventually written back from the cache to memory, when the cache line is needed for something else.
- In the next iteration of the above, the transmit buffer holds the data from the previous transaction.
There are two ways to solve this.
Set some memory aside for DMA buffers, and mark it as non-cacheable. I prefer this one, because it has to be set up once, and requires almost no attention later, and its effects can be resticted to the necessary memory area.
struct {
dma_rx[16];
dma_tx[16];
} nochache __attribute__ ((aligned (32)));
MPU->RBAR = ((uint32_t)&nocache) | MPU_RBAR_VALID_Msk; // using region slot 0
MPU->RASR =
MPU_RASR_XN_Msk | // 1: Instruction fetches disabled
(3u << MPU_RASR_AP_Pos) | // Full access
(4u << MPU_RASR_SIZE_Pos) | // 32 bytes
MPU_RASR_ENABLE_Msk |
0; // TEX,C,B,S are 0 meaning strongly ordered, this is the safest thing
The struct holding the DMA buffers must be padded and aligned to a power of 2, and at least to 32 bytes. If the size is changed, adjust the alignment attribute and the MPU_RASR_SIZE field accordingly. The full documentation of the MPU registers is in the PM0253 STM32F7 Series and STM32H7 Series Cortex®-M7 processor programming manual.
Cleaning and invalidating the cache when needed. This one can get tricky, especially at a DMA receive transaction.
There are 2 basic operations.
- Clean (or flush) writes back all modified data from cache to memory.
- Invalidate discards the contents of the cache without writing it to memory.
Preparing for a transmit is straightforward, just clean the cache before starting DMA.
Receiving is tricky, because invalidating means that a couple of preceding memory writes are lost. Therefore the cache should be cleaned immediately before invalidating, and it must be ensured that the receive buffer does not get accidentally cached. It must be aligned and padded to cache lines, cleaned before starting to receive, and not touched during receive. There are lots of ways it can go wrong.
