stm32f7 usart and data corruption

[Evan .1]

If I understand correctly the STM32F7 USART/UART doesn't have a hardware FIFO implemented. So how do I prevent data corruption if the interrupt aren't handled in time? Timing is now critical.

I see there a couple of examples which use DMA. Only how to use DMA with a big software FIFO. where counter needs to be updated after every read/write cycle?

So how is the intened use for this?

Thanks

[Piranha]

> you have 2 spi interface, 1 i2c 2 canopen implementation Ethernet data transfer,4 uarts

Let's make an approximation on worst case scenario of non-DMA (except for Ethernet) implementation. You have a 200 MHz CPU and 10 peripherals each generating 10 kHz of interrupts, which gives 100 kHz total interrupt rate. That means you have to be able to process each interrupt in 2000 CPU cycles.

Actually I once tried feeding SAI with stereo 48 kHz 24-bit stream using only interrupts on F7. As 24-bit stream requires 32-bit words, the interrupt rate was 96 kHz. At full 216 MHz clock speed that code added approximately 10 % of CPU load (including interrupt enter/exit and RTOS context switch times) and worked flawlessly. From that we can also deduce that the interrupt code took approximately 200 clock cycles.

That is completely viable with interrupts, and even more viable if DMA are used for at least some peripherals. You only have to... not use ST's brainless code-monkey made non-working bloatware named HAL/CubeMX and make decent driver, OS/platform and application level code.

[Tilen MAJERLE]

​ @Evan .1​ ,

I have prepared an example with some explanation how to implement DMA on RX and how to use it for data processing:

https://github.com/MaJerle/stm32-usart-uart-dma-rx-tx