stm32f7 FMC async trouble

[Mike Rosing]

Posted on December 09, 2017 at 16:43

I have set up the FMC with the following:

  /* Initialize the SRAM controller */

  RCC->AHB3ENR |= 1;  // turn on FMC

  BSP_LED_Toggle(LED3);

  FMC_Bank1->BTCR[0] = 0X00001081;

  FMC_Bank1->BTCR[1] = 0X00070607;

/*  initialize FMC I/O bus  */

  RCC->AHB1ENR |= 0X78;  //    turn on D, E, F and G

  BSP_LED_Toggle(LED3);

  GPIOD->MODER =  0xa000080a;

  GPIOD->AFR[0] = 0x00c000cc;

  GPIOD->AFR[1] = 0xcc000000;

  GPIOE->MODER =  0x002a8000;

  GPIOE->AFR[0] = 0xc0000000;

  GPIOE->AFR[1] = 0x00000ccc;

  GPIOF->MODER =  0xaa000aaa;

  GPIOF->AFR[0] = 0x00cccccc;

  GPIOF->AFR[1] = 0xcccc0000;

  GPIOG->MODER =  0x0000002a;

  GPIOG->AFR[0] = 0x00000ccc;

I am only using the NWE signal to latch data into an FPGA.  The bus speed is slow, with 21 clocks per transaction.  When it sends data, the timing looks ok.  The problem is there is no data transmitted until the address gets into the range of 0xa00.  The data on the data bus seems ok because sending 0x69 shows up on the data bus correctly when viewed on a 'scope.

I tried turning off the FIFO, but it did not make any difference.  The address bus is firing, but no data comes out for addresses below a certain point.  Since data does come out, the FMC seems to be set up correctly - but why is there no data below a certain point?

Mike

#fmc #async

[waclawek.jan · Accepted solution]

Posted on December 09, 2017 at 20:02

Cache?

JW

[Mike Rosing]

Posted on December 09, 2017 at 21:14

Good idea to look at - I am not familiar with how the FMC would react with that.  But it seems more address related - when I start at 0x000 I see lots of address toggling on the FMC address lines and not data for a long time.  When I start at 0xa00 the data starts toggling within 32 or so addresses.  I have not read up on the cache, sounds like a good thing to check out.

Mike

[Mike Rosing]

Posted on December 09, 2017 at 22:03

First try - turned off both instruction and data cache, and now it outputs at address 0.  I'll have to understand how that works now, but thanks for the clue!

Mike

[Mike Rosing]

Posted on December 09, 2017 at 23:15

So data cache was definitely the culprit.  I converted the test to use DMA from SRAM to FMC, and that works really well.  The bus transactions are uniform with 15 MHz rate.  Slightly faster than I need, but should work just fine.  I think MPU to SRAM does not have the same problem with stale cache because it has a different policy according to the manual.  In any case - THANKS!

Mike