STM32F7 Configurable Interrupt Priority levels

[dheerajdake9]

Hello ST,

From datasheet(PM0253),

The SHPR1-SHPR3 registers set the priority level, 0 to 255 of the exception handlers that have configurable priority.

Also from datasheet,

Each PRI_n field is 8 bits wide, but the processor implements only bits[7:M] of each field, and bits[M-1:0] read as zero and ignore writes.

What is the value of M? How does this relate to Binary point priority grouping?

Thanks

Dheeraj

[dheerajdake9 · Accepted solution]

I got the answer for this. The value of M depends on the value of priGroup set in AIRCR register. The range is described in Priority Grouping table 56. For example, if PRIGROUP is 0b001, M is 2.