How does STM32G4 Series FDCAN Tx Queue Addressing work?

The STM32G4 Series Reference manual RM0440 states in section 44.3.3 Message RAM → Tx Queue on page 1965:

A Tx Queue Buffer allocates eighteen 32-bit words in the Message RAM. Therefore the start address of the next available (free) Tx Queue Buffer is calculated by adding four times the Tx Queue Put Index TXFQS[TFQPI] (0 ... 2) to the Tx Buffer Start Address TBSA.

When a Tx Queue Buffer allocates eighteen words (72 bytes), why does one get the next address at an offset of four times the index, instead of seventy-two times the index?

EDIT

The HAL function `static void FDCAN_CopyMessageToRAM()` uses the following line to calculate the address:

 /* Calculate Tx element address */
 TxAddress = (uint32_t *)(hfdcan->msgRam.TxFIFOQSA + (BufferIndex * SRAMCAN_TFQ_SIZE));

SRAMCAN_TFQ_SIZE expands to 72:

#define SRAMCAN_TFQ_SIZE (18U * 4U) /* TX FIFO/Queue Elements Size in bytes */