stm32f407 i2s interface sync in slave mode

[albert2]

Posted on July 17, 2015 at 10:58

Hello, I'd like to know if there is a 'magical' way to syncronize the bit stream with the channel signal in the i2s receivers. I don't have control on the external stream ( slave mode), so the serial clock is free running, and the only way I've found to use the interface is to wait for the correct time to enable it.

Perhaps there is some way to do it using the receiver but I've been unable to find it.If this is a 'feature', perhaps it would be wise to modify the silicon on next iterations/products to allow for an automatical way to sync the receiver with the data stream.Thank you very much.Albert #i2s #stm32f407 #sync

[HoRyong Kang]

Posted on May 08, 2018 at 01:31

What do you mean '

inactive level of WS'?

Is it 0V or 3.3V level? 

[waclawek.jan]

Posted on May 08, 2018 at 07:35

My MCU is STM32F105RB

From ES022:

JW

[HoRyong Kang]

Posted on May 08, 2018 at 17:06

waclawek.jan you are right.

The WS sync is correct when the I2S is enabled at WS high level.

void I2S_Fit()

{ __disable_irq(); I2S_Cmd(SPI2, DISABLE); Init_I2S(); while(!I2S_WS_IN_PIN_READ); while(I2S_WS_IN_PIN_READ); while(!I2S_WS_IN_PIN_READ); SPI2->I2SCFGR |= 0x0400;//enables I2S

__enable_irq(); 

}

The I2S interrupt timing is not exactly same with the timing of I2S clock count.

So I have not realized the I2S data is correctly received.

There is no I2S WS sync bug at STM32F105RB.

STM32F105RB is excellent MCU.

Thank you , 

waclawek.jan.

and also Thank you Albert Gonzalez.