2024-04-27 12:24 AM
2024-04-28 01:46 AM - edited 2024-04-28 01:50 AM
Before switching to faster clock, you need to set FLASH waitstates. [EDIT] I overlooked you do that at the beginning.
If HSE=8 and PLLM=2, input to PLL is 4MHz which is outside its maximum (2.1MHz, see PLL characteristics in datasheet).
[/EDIT]
JW
PS. Style:
- use symbols from the CMSIS-mandated device headers, don't invent your own headers
- don't gradually OR values into registers, do that at once with one single write, either ORing all values into one single expression, or performing any calculations in a temporary value. Prefer direct writes (i.e. not read-modify-write, RMW); if you have to use RMW, again, read into temporary, perform any operation needed, and write back in one write.
2024-04-28 04:28 AM - edited 2024-04-28 04:30 AM
Can a 24-bit down count hold 32000000-1 ??
Probably want to use the DIV8 source
2024-04-28 06:46 AM
Thanks.
Yes, that was a mistake. I changed the main clock to run at 8MHz and the reload value to 8000000-1 . Still, facing the same issue
2024-04-28 06:53 AM
Thank you.
Now, I changed the PLLM=8, PLLN=16, PPLP=2. Changed the reload value of the Systick counter to 8000000. Still facing the same issue.
2024-04-28 10:23 AM - edited 2024-04-28 10:25 AM
> I also used a logic analyzer to check the period and it was not 1 sec.
[...]
> Still facing the same issue.
So, how much is it exactly?
If the Systick interrupt occurs once per second, and you toggle an output pin in that interrupt, the period is *two* seconds.
If that does not explain your problem:
Read out and check/post content of relevant RCC and SYSTICK registers.
What is the primary clock source? Is it a 8MHz crystal? Is it a crystal oscillator? Or any other source?
Output HSE (or its fraction) to MCO and check frequency there.
JW