2023-10-08 07:00 AM
Hi, I have STM32F407VET6 which has such memory layout.
Can I join SRAM (0x2000 0000 - 0x2001 BFFF) and SRAM2 (0x2001 C000 - 0x2001 FFFF) memories to one?
Or do I must to manage them separately?
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2023-10-09 02:04 AM - edited 2023-10-09 02:04 AM
I've just tried unaligned writes and reads across the 0x2001C000 boundary on an STM32F407, and it works as expected.
In other words, you can fully treat the two SRAMs as one.
JW
2023-10-08 11:39 AM
> Can I join SRAM (0x2000 0000 - 0x2001 BFFF) and SRAM2 (0x2001 C000 - 0x2001 FFFF) memories to one?
Yes.
JW
2023-10-08 11:42 AM
Just to be more specific: there wont be any issues/errors if the same object or DMA buffer overlaps combined SRAM and SRAM2?
2023-10-08 11:42 AM
This area on the F2/F4 parts can be described to linker as a single linear region of 128KB in size.
As I recall there was perhaps a usage as a USB related buffer for the upper 16KB
2023-10-08 11:47 AM - edited 2023-10-08 11:52 AM
> there wont be any issues/errors if the same object or DMA buffer overlaps combined SRAM and SRAM2?
Maybe unaligned access from processor across the boundary would be problematic, so avoid using unaligned objects (packed structs or data accessed through type punning) at that area. DMA can't make unaligned accesses.
The reason why are there two separate SRAM areas is, that two busmasters (processor, DMA, OTG_HS, ETH) can access the two separate memories at the same time with no timing penalty. Only in very extreme cases would this make noticeable difference.
JW
2023-10-09 02:04 AM - edited 2023-10-09 02:04 AM
I've just tried unaligned writes and reads across the 0x2001C000 boundary on an STM32F407, and it works as expected.
In other words, you can fully treat the two SRAMs as one.
JW