2025-01-27 02:33 AM - last edited on 2025-01-27 02:45 AM by Andrew Neil
In "Memory Mapping" section of the datasheet, the SRAM2 Address is indicated as 0x2001-C000.
The actual Address should be 0x2000-C000 since from what the reference manual says, both SRAM1 and SRAM2 are mapped at 0x2000-0000.
AHB1 Bus address has a missing digit, 0x4002-000
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2025-01-27 02:47 AM - edited 2025-01-27 02:56 AM
Hello @Fabx and welcome to the ST Community.
For the missing digit on the address of the AHB1, I've report it internally for correction (under internal ticket number 201440). For the SRAM limits, I think it is correct since what the RM0090 mention: " SRAM1 and SRAM2 mapped at address 0x2000 0000 and accessible by all AHB masters." that should mean that SRAM start at address 0x2000 0000 with SRAM1 then SRAM2 as you can see on the table 3 of the RM0090:
Thank you so much for your contribution.
Best Regards.
STTwo-32
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2025-01-27 02:47 AM - edited 2025-01-27 02:56 AM
Hello @Fabx and welcome to the ST Community.
For the missing digit on the address of the AHB1, I've report it internally for correction (under internal ticket number 201440). For the SRAM limits, I think it is correct since what the RM0090 mention: " SRAM1 and SRAM2 mapped at address 0x2000 0000 and accessible by all AHB masters." that should mean that SRAM start at address 0x2000 0000 with SRAM1 then SRAM2 as you can see on the table 3 of the RM0090:
Thank you so much for your contribution.
Best Regards.
STTwo-32
To give better visibility on the answered topics, please click on Accept as Solution on the reply which solved your issue or answered your question.
2025-01-27 03:01 AM
Thank you for the reply and the insight, i am currently following a embedded course and there was a discrepancy between the addresses, so i wanted to be sure that the address was correct before making any mistakes, or if i needed to update my documentation.