STM32F2 ADC Signal Noise

[mbleha9]

Posted on October 28, 2011 at 12:00

I have just tested my second design with STM32F2, now it is STM32F207ZFT6, the ADC behaviour is the same as in my first application - strong noise in ADC signal.

Essential part of the board schematics :

http://www.sendspace.com/file/si46gl

Board photo :

http://www.sendspace.com/file/45n68v

Noise of  current input without any signal connected : 

http://www.sendspace.com/file/totkwn

The same input noise with the CPU analog pin shortcircuited to GND : 

http://www.sendspace.com/file/cjagfy

Note : In the signal graphs above,  the vertical axe is in ADC-bits, not in volts!

; don�t be confused by its legend �[V]�, for this test we have used our modified program to see rough ADC data.

There are permanent spikes over 30 LSBs and more in the sampled signal, although they shouldn�t exceed 5-10 LSBs, by my opinion.

Another details :

• 2-side PCB, on the bottom side there are another connections but most of it is poured with GND signal - common for both digital and analog, the analog ground is not separated. As the board consumption is minimal, below 100 mA,  I think it should not cause such noise.

• voltage reference VREF 3.3V buffered by opamp, blocked by 100nF and tantallum 10uF in parallel, the same with VREF/2;  each of the processor power pin is blocked with 100nF cap

• in our older application we used the same design concept, but the processor used was AduC834; it has 12-bit ADC too and the signal noise was several LSBs only, there were no problems; main difference was that the AduCs internal voltage reference was used, no external one
• we have tested to disconnect processor analog ground pin from the board common GND and to connect it with extra wire directly to the voltage reference VREF ground, no effect
• it is three-phase network measuring device, there are 3 analog voltage channels and three current channels with switchable gain preamplifier; the CPU oscillator 25 MHz, internal clock 120 MHz by PLL, ADC-clock is 30 MHz(in compliance with techspecs), we have tested to slow main internal clock (therefore all secondary clocks too) downto one quarter, but without any effect
• ADC samples periodically input signal with rate 128 conversions per 50 Hz network period, i.e. each 156 usecs; results are transferred by DMA into internal RAM; data from the RAM are transferred via insulated RS485 (on another board) and visualized in our program. We have tried to prolong conversion times to maximum, no effect
• excluding CPU, there are only

  3 opams, 2 analog switches, I2C thermometer and three  ULN-switches(unused during test), powered by linear LF33 stabilizer, normally powered by 5V DC from switcher on another board, but during the test the switcher was disconnected and the LF33 was powered from clear laboratory 5V DC supply. I am sure nothing but the processor oscillator can oscillate on the board.

• checking  the signal with oscilloscope doesn�t get decisive results, the signal is too weak

 Anybody with this processor family ADC performance experience

?

#stm32f2-stm32f4-a/d-noise #adc-noise

[infoinfo989]

Posted on November 03, 2011 at 22:52

It certainly looks like you're setting up the GPIO pins correctly for analog input.

Agreed, 10 mV noise is very difficult to measure with an oscilloscope. Still, I would guess that what you're seeing is probably real. The actual peaks are probably a bit higher. Note that with a 3.3V Vref and 12 bits, one LSB corresponds to 0.8 mV. So 30 LSBs means 24 mV. You might try shorting out R59 - make it zero ohms. Note that according to the F2x datasheet, I(vref) = 220 uA max. V = IR = 220uA x 100ohms = 22 mV   This might not be your problem, but it's an easy thing to try. (Man this forum is brutal - it's taken me 3 attempts to post this.)

[mbleha9]

Posted on November 04, 2011 at 13:00

The VREF voltage level shouldn't depend on the R59 because being controlled by the U19A opamp feedback; the resistor limits opamp's capacitive load, as I know such load character is not optimal for opamp performance generally.Nevertheless, we tried both 10 Ohms and shortcircuit, but noise stayed unchanged.

Another test with external oscillator switched-off (running on the internal one) without any effect too. I am afraid that as all of analog filtering attempts failed we will have to try digital signal filtering ...

[infoinfo989]

Posted on November 04, 2011 at 17:16

To be honest, I wouldn't be going down the digital filtering route if I were you. The fact is, you have a noise problem on your board, and it's happening in a ''benign'' environment on your bench. I would expect it highly likely that this noise problem, if not properly fixed, is going to become substantially worse once you put your board into its final system, where (I assume) it's going to be subjected to much more external noise (stronger EM fields, more connectors or cables hooked up, etc) than it currently is on your bench. My concern is that any digital filtering you do to mask the noise problem on your bench is then going to have to be much greater to mask the noise problem in your final system. And that filtering can also filter out real things you might well want to measure.

The other I've learnt is that there's usually a strong correlation between board noise and radiated noise. If this is going to become a sellable product and will need to pass FCC or CE testing, then, in general, anything you can do to reduce board noise (like proper groundings etc) is often beneficial to reducing radiated noise as well. It appears from your schematic snippet that there are also some digital sections on the board - it shows what appears to be an address bus, a data bus and an ''OUT'' bus, an LCD interface, ethernet, etc. Lots of digital stuff that can contribute to EMI and would benefit from a quieter board. Don't let me tell you how to run your business, but that's my concern, if you attempt to digitally filter out noise that you don't currently understand the source of. It'll quite probably get worse as you integrate the board into a final system. The next thing I would try is a suggestion I've been holding off until now, because I know it can be several hours of work. And that's to make a proper solid ground plane for your board. The challenge you'll have with this is you've poured a 3.3V on the topside of the board. So I'm guessing that on the top of the PCB you probably don't have a lot of GND ''planes'' to work with, so the soldering may not be easy. It'll be easier on the bottom of the PCB where you've already poured a GND. The objective is to make a ''solid as possible'' GND connection, both top and bottom, and with top & bottom tied together. One thing that works well is desoldering braid (desoldering wick). That woven copper stuff you use for soaking up excess solder. It's thick, very low impedance, soft and easy to bend and work. Use it like wire to connect your GNDs together, the more the merrier. These ''wires'' need to connect to the GNDs of your major components, as well as to each other. Wrap a number of them around the four edges of the board, to connect top and bottom together as well. You can also use copper conductive tape to help tie things together if you have some handy, and electrical tape to help stop the braid from touching things it shouldn't. Remember the objective is to create a ground plane, almost as if your PCB has magically become a 4-layer board containing an embedded ground plane. If you have a grounding problem, and it sounds like you might, putting a bit of effort into this might yield some dividends. I hope this helps. Good luck

[mbleha9]

Posted on November 07, 2011 at 15:56

You are right, off course, Take my idea of the filtering as an act of desperation …

J

.

One of my last applications was built with the AduC834, that is 8051 clone with 12-bit ADC. The same design approach with 2-side PCB and no problems with noise. But I admit there were no external address/data buses etc. and, therefore, more place for common ground area – it occupied nearly all of bottom side. But in the past, I had, for example, an application with another 8051 one, the Infineon’s 80C515 with external code flash memory and 2 SRAM chips and other peripheries such like LCD and LED display etc. and, despite of its common grounding was worse in compare with existing STM-design, I had never such problems with a noise. Therefore I am rather suprised now. 

We will try to short-circuit ground planes on the bottom side with a „shield sock“, I will write results here.

For now, we tried to place the board into an empty deskop PC-box to shield possible air-conducted radio signals, but without any effect to the noise. 

Another test : corresponding U1 and I1 signals, that are sampled simultaneously, were short-circuited to ground (near processor pins). Although noise still detected in both of signals, differences between the signals were below 5 LSBs, i.e. the signals have the same modulated noise on them.

[emalund]

Posted on November 08, 2011 at 15:57 low analog noise with a 2 layer board is a matter of luck. thu8s you get the different results ''luck is a fickle lady'' Erik

[mbleha9]

Posted on November 16, 2011 at 16:04

New testing.Typical noise of standard board is on Fig1 at

http://imgur.com/a/TU9RQ

. To confirm the problem is caused by wrong grounding, we have done following modifications :

• reinforced common grounding (modified board on Fig2 and appropriate noise on Fig 3). As I hadn't suitable shield sock, I used standard cable (not optimal, I know).

• separation of analog ground from the digital one and their mutual interconnection at the VSSA processor pin (Fig 4).

None of them helped. So I am rather afraid the problem can occur again even after redesign to 4-layer PCB …

The only noticeable effect was reached by measuring the VREF/2 signal via individual processor pin simultaneously with each voltage and current pair using the third processor ADC and substracting it from voltage and current signals – then modulated noise is reduced to about one half (at

http://imgur.com/a/EeqUo

, upper red graph=standard signal, lower blue graph=signal after measured noise substraction). But I cannot use the third ADC for noise measurement, I need it for another task, so this is not a solution for me.

[mbleha9]

Posted on November 16, 2011 at 16:12

At the Fig. 5 at

http://imgur.com/a/TU9RQ

, there is noise when system clock slowed from 120 MHz down to 25 MHz. The noise is lower, but neither solution for me.

[Danish1]

Posted on November 16, 2011 at 18:59

Here's a fresh thought:

You make a point of using NP0 capacitors around your op-amps, and are right to do so because they are not microphonic (i.e. they do not translate vibrations into voltages and vice-versa). But to decouple your Vref and Vref/2 you use ''unspecified'' 100 nF capacitors. If they are X7R then microphonic effects might _put_ noise onto those lines. Can you try replacing C73, C66, C51, C70, C65 by NP0 parts (and so probably only 10 nF to fit in the space)? Hope this helps, Danish

[mbleha9]

Posted on November 21, 2011 at 10:32

The caps above replaced with 10n NP0 parts. Furthermore, another 10n NP0 caps added in parallel with 9 100n caps blocking CPU digital 3.3V. But no change, the noise not affected :-(.

[ingwmeier]

Posted on February 04, 2012 at 14:43

I have the same problems with STM32F103 and STM32F100 Boards (posted it in Dec 11). ST seems to have problems with their ADCs on various silicon revisions of the STM32 family. I tested up to 30000 samples for max / min. My solution for STM ADC is: take 8 samples, get rid of the 2 highest values and the 2 lowest values and average the 4 remaining. This gives good results (if ADC sample rate allows it).. Or switch to another family.

Just got an evaluation board by NXP, they have excellent ADCs. Also TI Stellaris ADCs allow good results. Werner