STM32F2 ADC Signal Noise

[mbleha9]

Posted on October 28, 2011 at 12:00

I have just tested my second design with STM32F2, now it is STM32F207ZFT6, the ADC behaviour is the same as in my first application - strong noise in ADC signal.

Essential part of the board schematics :

http://www.sendspace.com/file/si46gl

Board photo :

http://www.sendspace.com/file/45n68v

Noise of  current input without any signal connected : 

http://www.sendspace.com/file/totkwn

The same input noise with the CPU analog pin shortcircuited to GND : 

http://www.sendspace.com/file/cjagfy

Note : In the signal graphs above,  the vertical axe is in ADC-bits, not in volts!

; don�t be confused by its legend �[V]�, for this test we have used our modified program to see rough ADC data.

There are permanent spikes over 30 LSBs and more in the sampled signal, although they shouldn�t exceed 5-10 LSBs, by my opinion.

Another details :

• 2-side PCB, on the bottom side there are another connections but most of it is poured with GND signal - common for both digital and analog, the analog ground is not separated. As the board consumption is minimal, below 100 mA,  I think it should not cause such noise.

• voltage reference VREF 3.3V buffered by opamp, blocked by 100nF and tantallum 10uF in parallel, the same with VREF/2;  each of the processor power pin is blocked with 100nF cap

• in our older application we used the same design concept, but the processor used was AduC834; it has 12-bit ADC too and the signal noise was several LSBs only, there were no problems; main difference was that the AduCs internal voltage reference was used, no external one
• we have tested to disconnect processor analog ground pin from the board common GND and to connect it with extra wire directly to the voltage reference VREF ground, no effect
• it is three-phase network measuring device, there are 3 analog voltage channels and three current channels with switchable gain preamplifier; the CPU oscillator 25 MHz, internal clock 120 MHz by PLL, ADC-clock is 30 MHz(in compliance with techspecs), we have tested to slow main internal clock (therefore all secondary clocks too) downto one quarter, but without any effect
• ADC samples periodically input signal with rate 128 conversions per 50 Hz network period, i.e. each 156 usecs; results are transferred by DMA into internal RAM; data from the RAM are transferred via insulated RS485 (on another board) and visualized in our program. We have tried to prolong conversion times to maximum, no effect
• excluding CPU, there are only

  3 opams, 2 analog switches, I2C thermometer and three  ULN-switches(unused during test), powered by linear LF33 stabilizer, normally powered by 5V DC from switcher on another board, but during the test the switcher was disconnected and the LF33 was powered from clear laboratory 5V DC supply. I am sure nothing but the processor oscillator can oscillate on the board.

• checking  the signal with oscilloscope doesn�t get decisive results, the signal is too weak

 Anybody with this processor family ADC performance experience

?

#stm32f2-stm32f4-a/d-noise #adc-noise

[infoinfo989]

Posted on October 29, 2011 at 18:17

Your post was interesting so I decided to perform some similar tests and see what we got.

Processor is a 217 running with its internal oscillator at 120 MHz. ADC is running at 7.5 Mhz clock (ie 60 Mhz / 8). Sampling rate is 8 kHz, 12-bit data. Both the processor and Vref are running at 1.8V, provided by a (common) linear regulator. The Vref & Vdda are fed their 1.8V through a ferrite bead and then a couple of caps. ADC input pin was shorted to ground. I grabbed 4000 samples and binned them. Samples of value 0 went in bin 0, samples of value 1 went in bin 1, etc. Here are the bin counts: adc_noise_levels results BIN[0] = 1081 BIN[1] = 1359 BIN[2] = 1296 BIN[3] = 229 BIN[4] = 33 BIN[5] = 2 BIN[6] = 0 BIN[7] = 0 etc (all remaining bins are zeros) You can see for yourself the highest level is 5 LSBs, with the bulk of the samples being 1 LSB. I've run this a few times - the numbers I've posted here are pretty typical. I never see anything above 5 LSBs. Looks like you've probably got noise in your board that's making its way into the ADC. First thing I would try is putting a ferrite bead in the +5V rail that's powering U19.

[mbleha9]

Posted on October 31, 2011 at 13:53

Hi Frank,

we have installed a ferrite bead into the U19 supply branch, no effect. ADC was clocked from 60 MHz/2, then we tested 60MHz/8 too, but nothing changed. In your application you have separated analog ground from digital one ? Where they are connected together ? Thank for your help, Milan.

[infoinfo989]

Posted on October 31, 2011 at 16:40

We have not separated analog and digital ground. We have a single solid groundplane, which everything connects to. More specifically, we have a 2-sided PCB, where the bottom is largely ground. The top has sections of ground pour, and the top and bottom ground pours are stitched together with plenty of vias scattered around the board.

If you've got a split ground plane, you might want to read this:

http://www.hottconsultants.com/techtips/split-gnd-plane.html

[mbleha9]

Posted on October 31, 2011 at 17:24

We have not separated analog and digital ground too. Bottom side is poured with common GND, the top side with +3.3V power.

But density of connections didn't allow to keep recommended rules of separation of digital and analogue traces. Nevertheless, I am surprised by the ADC noise level when you take in account that the only load of the board are drawn by CPU, i. e. some 100 milliamps, no external signals are connected and there are no other digital signals active excluding serial link. Therefore I am still not sure that the problem is in the board topology. But where ...

[infoinfo989]

Posted on October 31, 2011 at 19:14

Try to find a way, either in your PCB program or your gerber viewer, to ONLY look at the GND copper. If you've only poured GND on the bottom layer, and if you also have some traces etc on that bottom layer, plus vias popping through, you might have significant breaks in your GND. I've had problems in the past where I've had a row of vias, or a long connector or something, that's created a big break or hole in my ground plane, meaning that ground return currents have needed to make a detour to find their way home.

Also, I'm assuming that when you're doing your noise test with the analog input grounded, you have nothing else plugged into your board except for power.

[mbleha9]

Posted on November 02, 2011 at 10:08

The poured common ground is really not consistent, there are several “islands�? interconnected with short 30-60 mils wide traces and vias. So I admitted the problem is probably in topology.

To confirm this theory, I disconnected processor analog ground pin from the pcb common ground and wired it with separate wire to voltage reference ground pin. One of analog inputs was disconnected and wired to the same ground too. I left the VREF pin connected to the pcb unchanged – its trace to the VREF opamp nearby the voltage reference chip is several cm long, decoupled in the same place. As common point of analog and digital ground was now at the voltage reference potential, I supposed that if the ADC noise at original board was caused by interference of the CPU source current in common ground plane, it should be essentially reduced after described modifications and the scanned signal should get zeros or several more bits more only.

But nothing essential occurred, the signal got zero with modulated noise of 20-30 bits again. I note that we modified the program in the way the signal was scanned to the RAM first without any connected board or serial link, there was nothing on the board but the processor and opams and the board was supplied from laboratory DC power supply; then serial link was connected and previously scanned signal was transferred from the RAM to a PC. Therefore, possible injection of noise via serial link was eliminated.

I tried another board, behaviour of both is the same.

After your responses I was nearly decided to start the board redesign, but now I am confused and afraid that new design needn’t bring better results …

Have you another idea how to test the noise is caused by wrong grounding ? Or any tip ?

[raptorhal2]

Posted on November 02, 2011 at 22:18

Two thoughts:

Did you connect VREF- to VDDA close to the processor ? What noise levels does an oscilloscope show for VREF- close to the processor ? Cheers, Hal

[infoinfo989]

Posted on November 03, 2011 at 01:45

Just to check....

You do have the GPIO pins that you're using as A/D inputs configured for analog mode (register GPIOx_MODER) and not as input or alternate function, right?

[mbleha9]

Posted on November 03, 2011 at 10:31

1-

STM32F2 family chips have not separated “VREF-“ pin, it is connected internally with the VSSA analog ground pin. VDDA analog power pin is supplied from digital +3.3V power via LC-filter with  BLM31B601SPT ferrite bead chip and 100n cer.//10u tant. caps. The VREF+ signal from analog reference is decoupled similarly, then lead by approx. 5 centimeters long trace to the processor pin and here decoupled again with another 100nF cap in distance approx. 5 millimeters from the pin.

On oscilloscope there is noise about 10mVpp on both VREF+ and analog signal, but I am not sure if it is real signal or overall noise, it is too weak signal.

2-  GPIO setting rechecked again – example for 2 analog pins :

// Analog inputs U1, I1

  GPIO_StructInit(&GPIO_InitStructure);   GPIO_InitStructure.GPIO_Pin = GPIO_Pin_4 | GPIO_Pin_5;   GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AN;   GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL;   GPIO_Init(GPIOA, &GPIO_InitStructure);

We think it is correct. Other inputs are set similarly.