STM32F103 MDK-ARM5 NVIC can't change an address.

[tome]

Posted on October 13, 2017 at 12:55

Hello comunity,

I trying to write a bootloader that will copy firmware from one memory range to other. And I need your help with understanding what is going on with my STM32F106C8T6 and what I doing wrong.

Incoming data:

-bootloader      0x08000 0000

-KEY                0x08000 4c00

-FW_main       0x08000 5000

-FW_Source   0x08000 A000

i'ts start addreses for each part of my program.

Logic of program:

Bootloader starts and chek is the KEY-dada exist on the KEY addres.

Here two ways:

- If KEY-data exist - bootloader starts copying data from FW_Source memory range to FW_main memory range. After copying all FW_Source data, we clean KEY-data,  FW_Source-data and reboot. 

-If KEY-data data other way it jumps to the address FW_main + 4.

On this stage all what we should to know. 

Im using Keil MKD ARM 5 with HAL. When I want writing firmware to the address 0x08000 A000 I shoud to edit ProjectName.stc file

---

; *************************************************************

; *** Scatter-Loading Description File generated by uVision ***

; *************************************************************

LR_IROM1 0x0800A000 0x00010000 { ; load region size_region

ER_IROM1 0x0800A000 0x00010000 { ; load address = execution address

*.o (RESET, +First)

*(InRoot$$Sections)

.ANY (+RO)

}

RW_IRAM1 0x20000000 0x00005000 { ; RW data

.ANY (+RW +ZI)

}

}

---

Then I could to flush stm32f103 in the right memory ranege. I check it end everything is ok.

If after copying data from 

FW_Source   to 

FW_main  I 

didn't erase the

FW_Source 

memory rage. The aplication works as i expexted it's jump to the

0x080005000 and works fine. 

But! If I ereasing 

FW_Source  range it's stop worknig. 

So, as I understand I need to move NVIC table to the new address (0x08005000), as HAL don't have a function 

NVIC_SetVectorTable I deside to write it directly to the register SCB->VTOR = 0x08005000;  But, this didn't help me.

--- User aplication code ---

int main(void)

{

/* USER CODE BEGIN 1 */

__set_PRIMASK(1);

SCB->VTOR = 0x08005000;

//__set_MSP(*(__IO uint32_t*) 0x08005000); //-- ???? ?? ?????

__set_PRIMASK(0);

/* USER CODE END 1 */

...

---

Then, I tryed to comment data in the systeminit() (

system_stm32f1xx.c).But this also didn't help me.

---

&sharpifdef VECT_TAB_SRAM

SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */&sharpelse //SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */&sharpendif

--- 

Also I tryed set the SCB->VTOR in the bootloader jumb function, but and this didn't help.

---

void jumpToApplication(uint32_t addr)

{ typedef void (*pFunction)(void); pFunction Jump_To_Application; uint32_t JumpAddress;

JumpAddress = *(__IO uint32_t*) (addr + 4);

Jump_To_Application = (pFunction) JumpAddress;

SCB->VTOR = addr; //set NVIC table

__set_MSP(*(__IO uint32_t*) addr);

Jump_To_Application();}

---

I'm confused, while reading manuals I didn't finde anything that can explain why it's didn't work. So, community I need your help .

Best regards,

Sergii Kirichok 

#nvic #mdk-armv5 #stm32f1 #stm32 #bootloader

[Tesla DeLorean]

Posted on October 13, 2017 at 13:22

You need to build the code for the address you expect to run it at and not the address you park it at before copying.

The vector table contains absolute addresses. 

[tome]

Posted on October 13, 2017 at 15:08

Thank you for your answer.

You are right, I if build frimware with configured someproject.stc to the  0x08005000 adreses It works, I knew it before. But, while I testing (copying firmware from one segment to other) , I nedded to to flush it to one andress and run from other. I can't understand, what could to do liker, that can't be changed from the aplicaton.

[Tesla DeLorean]

Posted on October 13, 2017 at 15:39

Addresses described *IN* the Vector Table, not the tables address. 

[tome]

Posted on October 13, 2017 at 16:00

I thought that vector table is based on the 0x8000 0000 address and has it's own offset. Also it could be changed by adding offset.

---system_stm32f1xx.c----

&sharpifdef VECT_TAB_SRAM

SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */&sharpelse //SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */&sharpendif  

---

And it's has own offset for example 0x004 or 0x008

---- core_cm3.h ---

\ingroup CMSIS_core_register \defgroup CMSIS_SCB System Control Block (SCB) \brief Type definitions for the System Control Block Registers @{ */

/**

\brief Structure type to access the System Control Block (SCB). */typedef struct{ __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ uint32_t RESERVED0[5U]; __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */} SCB_Type;

...

---- 

[Tesla DeLorean]

Posted on October 13, 2017 at 16:31

Ok, but you don't seem to grasp that the Vector Table has content, you can place the vector table using SCB->VTOR, but it is the CONTENT of the Vector Table (ie the hundreds of entries describing the addresses of the IRQ Handlers) that have been fixed by the Linker.

Stick 0x0800A000 into the Memory View of the debugger in 32-bit Word mode and look at what is being described..

[Tesla DeLorean]

Posted on October 13, 2017 at 16:32 The original post was too long to process during our migration. Please click on the provided URL to read the original post. https://st--c.eu10.content.force.com/sfc/dist/version/download/?oid=00Db0000000YtG6&ids=0680X000006I6tl&d=%2Fa%2F0X0000000bxc%2FEjfdILPaPpRIqzWGyeQioErrPedaBymbQWFqS9DMUKM&asPdf=false

[tome]

Posted on October 17, 2017 at 12:31

Hi,

I got it.

Thank you for explanation and patience.