STM32F051C8T6 unable to enable PLL - resets [SOLVED]

[robbevanassche]

Posted on November 05, 2014 at 01:03

Hey,

I made a custom board with the STM32F051C8T6. Connecting via STLINK/V2 genuine. The chip is genuine, revision B. When i use this code:

#include <
stm32f0xx.h
> //stm32f030f4
#include ''stm32f0xx_rcc.h'' //we use rcc
#include ''stm32f0xx_gpio.h''
#include ''stm32f0xx_flash.h''
//connection
#define LED_PORT GPIOF
#define LED_A (1<<
6
)
#define LED_C (1<<7)
void SystemCoreClockHSIPLL2(uint32_t RCC_PLLMul_x) {
RCC_DeInit(); //reset rcc
RCC_PLLCmd(DISABLE); //disable PLL
RCC_HSICmd(ENABLE); //enable hsi;
RCC_HCLKConfig(RCC_SYSCLK_Div1); //set sysclk divider
//RCC_PCLK1Config(RCC_HCLK_Div1); //set pclk1/2 dividers
//RCC_PCLK2Config(RCC_HCLK_Div1);
/**
* @brief Configures the PLL clock source and multiplication factor.
* @note This function must be used only when the PLL is disabled.
*
* @param RCC_PLLSource: specifies the PLL entry clock source.
* This parameter can be one of the following values:
* @arg RCC_PLLSource_HSI_Div2: HSI oscillator clock selected as PLL clock source
* @arg RCC_PLLSource_PREDIV1: PREDIV1 clock selected as PLL clock entry
* @arg RCC_PLLSource_HSI48 HSI48 oscillator clock selected as PLL clock source, applicable only for STM32F072 devices
* @arg RCC_PLLSource_HSI: HSI clock selected as PLL clock entry, applicable only for STM32F072 devices
* @note The minimum input clock frequency for PLL is 2 MHz (when using HSE as
* PLL source).
*
* @param RCC_PLLMul: specifies the PLL multiplication factor, which drive the PLLVCO clock
* This parameter can be RCC_PLLMul_x where x:[2,16]
*
* @retval None
*/
FLASH_SetLatency(FLASH_Latency_1);
FLASH_PrefetchBufferCmd(ENABLE);
RCC_PLLConfig(RCC_CFGR_PLLSRC_HSI_Div2, RCC_PLLMul_x); //configure pll / divider. _x=[2..16]
RCC_PLLCmd(ENABLE); //enable pll
while (RCC_GetFlagStatus(RCC_FLAG_PLLRDY) == RESET) continue; //wait for pll to be ready
RCC_SYSCLKConfig(RCC_SYSCLKSource_PLLCLK); //set pll as sysclk
while (RCC_GetSYSCLKSource() != RCC_CFGR_SWS_PLL/*0x08*/) continue; //wait for PLL to be ready
SystemCoreClockUpdate(); //update SystemCoreClock
}
//delays some
void delay(uint32_t dly) {
while (dly--) __asm(''NOP'');
}
int main(void) {
SystemCoreClockHSIPLL2(RCC_PLLMul_12); //go to 48Mhz
RCC_AHBPeriphClockCmd(RCC_AHBPeriph_GPIOF, ENABLE);
GPIO_InitTypeDef gis;
gis.GPIO_Mode
= 
GPIO_Mode_OUT
;
gis.GPIO_OType
= 
GPIO_OType_PP
;
gis.GPIO_Pin
= 
LED_A
| LED_C;
gis.GPIO_PuPd
= 
GPIO_PuPd_NOPULL
;
gis.GPIO_Speed
= 
GPIO_Speed_50MHz
;
GPIO_Init(LED_PORT,&gis);
LED_PORT->ODR &= ~(LED_A);
LED_PORT->ODR |= (LED_C);
while(1) {
LED_PORT->ODR ^= (LED_A | LED_C);
delay(1000000);
}
}

The chip resets. the nRST pin is pulled low and the chip starts over again. In attachment is a view of the nRST line. This happens when ''

RCC_PLLCmd(ENABLE);'' is executed.

If i use a multiplier 2 or 3, the chip works and the nRST is not pulled low. The gpio pins toggle according to the clockfreq, so the program runs like it should. Anyone has an idea how to solve this ? #m0-pll

[waclawek.jan]

Posted on November 05, 2014 at 09:12

Inadequate power supply, inadequate routing of supply voltage/ground, inadequate decoupling... Have you tried the same code on a known-working hardware, e.g. EVAL or DISCO board?

JW

[robbevanassche]

Posted on November 05, 2014 at 11:13

Going through all possible routes in programming, i'm starting to think the same.

This code works with the STM32F0 discovery board. (Changed GPIO pins though).So yes, i'm going to focus my investigation into the decoupling caps.I've used 0402 MLCC's of 100nF and one tantalum of about 10uF.The datasheet suggested that i use an extra 1uF on the AVCC pin, which i didn't do.I'll rely with my findings tonight.Thanks for the help!

[robbevanassche]

Posted on November 08, 2014 at 18:38

Solved. AVCC was not connected.