STM32F$ DMA mapping

[stst9193]

Posted on March 01, 2015 at 12:00

I am a bit confused by the channel mapping description in '' DocID018909 Rev 8''  and would appreciate some addditional explanations.

In ''10.3.3 Channel selection''  we have the following text ''Table 42 and Table 43 give examples of DMA request mappings.''. Is there a different place where one can find and ''exhaustive''  list of possible mappings rather than an ''example''? In addtition some of the ''example mapping''  (e.g., DMA1, Stream 0 , channel 4) implies a '' unidirectional mapping'' (to UART5_RX) when all other descriptions consider that a stream can be programmed for either direction. Any hint on what is actually possible? Thanks Gerard  #stm32f4 #dma

[Tesla DeLorean]

Posted on March 01, 2015 at 13:26

The tables contain a complete matrix for connectivity, some STM32 manuals also have an OR gate representation of the ''channel'', ie multiple sources into a single stream

The connections are for triggers, ie USART1_TXE or USART1_RXNE The DMA stream may be programmed in either direction, different channel sources may have different expectations. ie USART1_TX will only clear if you write USART1->DR, but TIM1_UP could read or write a GPIO->IDR/ODR periodically.

[stst9193]

Posted on March 02, 2015 at 08:54

Thanks a lot.

Gerard