STM32 Timer 8 ETR pin behaving as output

[Jansunil]

Hello Team,

I am using an STM32F469NIH6 in my project and the following is my use case:

I need the timer 8 to act as a slave to its ETR pin, which is PA0. I have a signal coming out on the PG7 from my daughter board and I have connected PG7 and PA0 via a jumper. I also need the same timer to trigger a timer DMA transaction upon overflow/ CC

My observation is that the timer 8 is getting triggered well and the DMA transaction is also happening well. But the signal that my daughter card sends out on the PG7 holds a different duty ratio. ie- the ETR pin is actually sending out some signal, which is corrupting the signal on PG7.

In the present case, I am also setting the PA15 (SPI1 Chip select) low for initiating the SPI DMA transactions. The signal integrity issue is seen only when the DMA is triggered while PA15 is set low. Things look fine when PA15 is high

Here are my register values:

Any leads on this would be of help.

Thank you,

Janani

[Sarra.S]

Hello @Jansunil 

What you can do is try to isolate the issue

Disable SPI DMA and observe if the signal integrity issue on PG7 persists 

Also, could you share some oscilloscope screenshots that probes the signals on PA0 and PG7 to visually inspect any noise

[Jansunil]

Hi @Sarra.S  Thank you for your reply.

Upon disabling the DMA channel that is responsible for triggering the Tx transactions, ie the TIM8 CH2 DMA request, this issue isn't seen. 

Its only when I enable the TIM8->DIER |= 1 << 10 (this sets the CC2DE) and lower the CS (PA15) together, this is seen.

I have attached some Screenshots of waveform with the register values. There are three stages:

1) Before CS Low

2) CS Low without DMA trigger

3) CS Low and DMA trigger

Stage 3 is when the PA0 signals are getting corrupted.

   

[Sarra.S]

Given this new information; that the issue occurs only when both the TIM8 CH2 DMA request is enabled and the (CS) on PA15 is set low, this may be a timing or resource conflict! 

If you have the same DMA priority level in both the SPI and Timer 8 transactions, consider changing the priority to give the SPI transactions a higher priority

Also, I suppose you're not using the same DMA stream! 

[Jansunil]

@Sarra.S - You are right- the issue occurs with the TIm8 CH2 request enabled and the PA15 reset together.

I did try to play around with the DMA priorities- didn't help

I am using different DMA streams for both. 

What do you suggest in this case?