STM32 H745. Is it possible to trigger a dma transfer from memory to SPI on rising/falling edge of pwm generated from a timer?

[EDallaVia]

Hello, I'm having trouble reading from external ADC which needs a maximum time of 10ns from the falling edge of command (I'm giving it from a TIM4 PWM mode 1, 300ns active, 100kHz frequency). I'm using TIM3 as a slave timer from TIM4, one shot and TIM3_UP to generare SPI TX (just to generate the clock to read the data from the ADC). But I can't find the correct event for TRGO of TIM3 to achieve what I need. Update is not good because I've got it at the end of the PWM (2ms), I can't use ENABLE because the TIM4 is always running, TIM4 RESET has no effect either. Any suggestion?

Many thanks

Enrico

[waclawek.jan]

Why don't you trigger the DMA transfer from some of the TIM4's other channels, set to output compare (PWM) with a suitably shifted compare time, without actually having assigned a pin in GPIO?

JW

[gbm]

You may trigger the DMA by any compare event from any of CCRx registers - see the DMAMUX source table.

[EDallaVia]

thanks for the answers. After througholy reading the manual of the ADC, it seems I misunderstood the requirements of 10ns (it the maximum time after another line goes down for the data to be ready to be read). I'll try to reduce the speed and see if the misbehaviour I've got are still present because right now I've got on the memory a lot of duplicate data instead of a neat sampling value (means the value are in some way correct because they follows the waveform in the input, but I've got 4 data at same value before new different value is received and so on). D-cache is disabled.