STM32 H7 - SPI CLK behaviour at high frequencies

[JCori]

Hello everyone, 

I'm reaching out to seek guidance in pushing the SPI CLK line output to, at least, 65 MHz.

In theory, this should be possible according to the Reference Manual by setting the GPIO speed to Very High in Vdd = 3.3. 

Currently, I am able to drive the signal at 40MHz and still get a decent square signal with a bit of over and undershoot, however, pushing above these speeds causes signal degradation and distortion. The rise/and fall times for the wave seem to be too slow, causing further problems.

I've tried enabling the cell compensation with a sequence similar to the one below as per the Reference Manual

RCC->CR |= RCC_CR_CSION; // turn on CSI
while(!(RCC->CR && RCC_CR_CSION_Msk)); // wait for the CSI to come online

SBS->PMCR &= ~(SBS_PMCR_BOOSTEN);
SBS->PMCR |= SBS_PMCR_BOOSTVDDSEL; // reduce harmonic distortion

SBS->CCCSR |= (0 << SBS_CCCSR_COMP_CODESEL_Pos) | SBS_CCCSR_COMP_EN;
while(!(SBS->CCCSR & SBS_CCCSR_COMP_RDY)); // wait until the cell is ready to go

I have also tried fine tuning the SW cell value by iterating and writing to 

SBS->CCCSR |= (0 << SBS_CCCSR_COMP_CODESEL_Pos) | SBS_CCCSR_COMP_EN;

// clear the values for P/NMOs
SBS->CCSWVALR = 0x00 << SBS_CCSWVALR_SW_PSRC_Pos;
SBS->CCSWVALR = 0x00 << SBS_CCSWVALR_SW_NSRC_Pos;

// pass the new value
SBS->CCSWVALR = pmos_val << SBS_CCSWVALR_SW_PSRC_Pos;
SBS->CCSWVALR = nmos_val << SBS_CCSWVALR_SW_NSRC_Pos;

 The GPIO speeds are set to the maximum speed, I am sending 4 bits through the HAL SPI API and there is no load in my circuit, this is being measured straight out of the pin of the Nucleo-144 dev board. 

HAL_SPI_Transmit(&hspi1, &pData, 4, 100);
HAL_Delay(1500);

Another thing to note is that, during testing, changing the speed of the GPIO did not have major effects other than reducing the overshoot minimally, except on slow mode, in which there was complete signal loss. 

I should mention I also tried adding a load to the pin's output (a small RC circuit,20 ohms and 40 pF) to dampen the overshoot and comply with the Reference Manual's specifications.  While this did help with the overshoot, it did not changed the slew rate's behaviour .

I will very much appreciate any help anyone can provide!

[TDK · Accepted solution]

Is your probe in 10:1 mode? 1:1 mode adds much more capacitance.

> Nucleo-144 dev board

This board has long traces that aren't going to be amenable to high speed signals, especially once you cable them out to where you want them to go. Expect to be limited to 1-10 MHz.

Lay it out on a new board with good routing and these problems will disappear.

[AScha.3]

Hi,

which cpu ?   

I have H743ZIT , H7A3Z , H733 ...H563Z , ...

SPI on H743 can have a clock up to 100M :

If pin speed set to very high , pin will switch fast - really fast :

110M , but at 10pF load ! So if you connect your (standard ? ) probe, at 10:1 setting, it will add about 10pF load to the pin/line....You cannot measure it with a standard probe and a scope.

Just believe the ds: it IS switching at ~ 3ns rise/fall times, but your connection has to be short, damped with a series resistor and low capacity...if you connect a cheap standard probe - its "game over".

[JCori]

Hi,

I'm working with the H7S3L8, also, my digital oscilloscope is 200 MHz rated, using a 10:1 probe also rated for 205 MHz, so I believe in terms of capacitance this should be within range. I even tested this with a 500 MHz rated scope. 

I added a 100 Ohm resistor to the load and I am able to see a more clean signal at 100 MHz, but the fall and rise time are still an issue.

I agree that datasheet specifies the performance conditions, but my testing probe seems to be within the bounds of the specification. So, considering @TDK's comment as well, could the traces on the board be adding enough capacitance to see such a decrease in the signal's quality and time response? 

Thank you for the help.

[LCE]

Do you use the probe's standard GND connection with the ~ 10 cm cable ?

I guess you do, so don't... try a spring tip for GND directly at the probe's tip and find a very close GND connection (e.g. a STM32 pin, or VCC capacitor, or scratch of some solder resist if you have a top GND plane).

I have a very similar Tektronix scope, and so many overshoots disappear and flanks are much steeper when measuring the right way.

[TDK]

If you measure on the actual STM32 pin or pad and use a spring clip to a nearby VSS pin it will likely look much better.

[JCori]

Hi LCE,

Thanks for the tip! Yes, I also tried the spring tip to test the CN12-11 and CN12-9 connectors (which are conveniently next to each other) to test the CLK output, sadly the overshoot persists. 

I am wondering if there's any software setup I may have missed.

Thank you for the input!

[LCE]

Okay, but is there some kind of load and / or termination ?

And: the Nucleo's PCB layout is terrible for many signal lines, especially those going to the connectors.
Looks more like made for I2C or so with max 1 MHz.

[JCori]

Yes, a resistor, which does diminish the overshoot. 

We ran a couple more tests by actually cutting off one of the lanes and testing directly at the chip's output. This resulted in observing much better rise and fall times and evidenced the circuit's susceptibility to capacitance. 

Thank you everyone for your responses. 

[AScha.3]

>I am able to drive the signal at 40MHz and still get a decent square signal

Fine, so you know: your probe+scope working fine at 40 MHz , square wave = to see a 40M square, you need at minimum 3. and 5. harmonic, thats 200MHz !

So everything fine - except your expectation, to live not in our universe and its physics.

To see something like a 100MHz sine, you can use your probe+scope , as this is in its capabilities.

For 100MHz square, at least with 3. and 5. harmonic, you need a > 500MHz probe+scope.

To see a real good square, need 9. harmonic minimum, so a > 1GHz probe+scope would be needed.

And ultra low capacity probe, with < 20mm wires signal AND ground to probe...really difficult and expensive.

OK now , understanding ?