STM32 H7 - I2S Clock Timing Problems (runs at 1.027 Mhz for some reason) - See PulseView

[AnkhInnovationsLLC]

Hello,

Still trying to get I2S working on the H7...

Opened up PulseView to check the clock between another connected device...

Much to my surprise, the STM32 is actually outputting 1.027 Mhz average clock pulses instead of the ESP32's 1.024 Mhz. 

Checked the Clock in STM MX, shows 0% error and an input clock of 2.048 Mhz which is divisible. Tried also 20.48 Mhz with no change. There appears to be no divider settings. Any reason for this wrong output clock?

There are many "Expected 16 bit word, received 17 bit" etc, with varying bits because of the wrong clock. Expected is 16 bits.

[Piranha]

The targeted 16 kHz sample rate in the screenshots points to this solution not requiring a Hi-Fi audio. Anyway I would avoid using PLL in fractional mode unless actually necessary. I the latest screenshots the author has already found the best rational fraction for PLL, which deviates from the ideal frequency by +11 ppm. Humans can detect a pitch variation of 0,3 % (3000 ppm) at best. And that is for a variation, not a constant offset! In other words - there is absolutely no point in using a fractional PLL mode and increasing the jitter unnecessarily.