Hi @Community member ,
thank you very much for your reply ��
About PWM mode 1: I found the same in the reference manual on page 510 as you described. So I agree that I have to change the Capture/Compare 1 output polarity to high (the initial value is all zero of the register so I don't need to write a value or am I wrong? Please apologize but this is my first projekt with a microcontroller). But it is the oposite of what is written in the timer cookbook (maybe a mistake in the file).
The good news is: the output polarity is high while CNT < CCR1 and low when CCR1 <= CNT <= ARR.
The bad news is: after TIM1 reaches the value of ARR and waits for the next trigger of TIM2 (master) the output polarity change to high while idleing �� . I thought if TIM1 finishes the output gets disabled and the output polarity is low as described in figure 35 in the timer cookbook. So how can I fix this?
About your remarks (just for clarification as I'm from Germany and maybe there could be a loss of translation on my side.
1.) If I get this correct and look at my code of the slave mode configuration I should write "TIM1->SMCR |= (TIM_TS_ITR1 | TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1);" instead of "TIM1->SMCR |= TIM_TS_ITR1;" and "TIM1->SMCR |= (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1);"?
So the code where I reset the value of the specific bits in the registers is also not necessary as the register is all 0x00 initially?
2.) OK so for example I changed "TIM1->CCMR1 |= TIM_OCMODE_PWM1;" to "TIM1->CCMR1 |= (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1);".
So my code looks finally like this with regards to you remarks (hope I did everything as described by your remarks. If not I would be really happy about a little snippet):
void timer1_Init(){
/* TIM1 is on APB2 with clock speed 180MHz */
/* activate clock for TIM1 peripheral */
__HAL_RCC_TIM1_CLK_ENABLE();
/* neue Struktur */
/* Prescaler */
TIM1->PSC = 35999;
/* Auto-Reload-Register */
TIM1->ARR = 19999;
/* repetition counter if pulse should be displayed more than 1 time */
TIM1->RCR = 1;
/* Set the Capture Compare Register: Pulse */
TIM1->CCR1 = 4999;
/********** Control Register 1 **********/
TIM1->CR1 |= TIM_CR1_OPM; //setze das dritte Bit
/********** Capture Compare Mode Register 1 **********/
/* Select the Output Compare (OC) Mode */
/*
* Mode 1: In upcounting, channel 1 is active as long as TIMx_CNT<TIMx_CCR1
* else inactive. In downcounting, channel 1 is inactive (OC1REF=‘0’) as long as
* TIMx_CNT>TIMx_CCR1 else active (OC1REF=’1’).
*
* Mode 2: In upcounting, channel 1 is inactive as long as TIMx_CNT<TIMx_CCR1
* else active. In downcounting, channel 1 is active as long as TIMx_CNT>TIMx_CCR1 else
* inactive.
*/
TIM1->CCMR1 |= (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1);
/* Set the Output Compare Preload enable bit for channel 1 */
TIM1->CCMR1 |= TIM_CCMR1_OC1PE;
/********** Slave Mode Control Register **********/
/********** Slave Mode configuration: Trigger Mode **********/
TIM1->SMCR |= (TIM_TS_ITR1 | TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1);
/*************************************************/
/********** Event Generation Register **********/
/* update event to reload registers - set the UG Bit to enable UEV */
TIM1->EGR |= TIM_EGR_UG;
/********** Break and Dead Time Register **********/
/* Enable the TIM1 Main Output */
TIM1->BDTR |= TIM_BDTR_MOE;
/********** Capture Compare Enable Register **********/
TIM1->CCER |= TIM_CCER_CC1E;
/* Initialization of GPIO_PIN_8 for PWM output */
GPIO_InitTypeDef GPIO_InitStruct = {0};
__HAL_RCC_GPIOA_CLK_ENABLE();
GPIO_InitStruct.Pin = GPIO_PIN_8;
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
GPIO_InitStruct.Pull = GPIO_PULLUP;
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
GPIO_InitStruct.Alternate = GPIO_AF1_TIM1;
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
}
void timer2_Init(){
/* TIM2 is on APB1 with clock speed 90MHz */
/* activate clock for TIM2 peripheral */
__HAL_RCC_TIM2_CLK_ENABLE();
/* Prescaler */
TIM2->PSC = 44999;
/* Auto-Reload Register */
TIM2->ARR = 19999; //19999;
/* Update Event - if this timer is configured as Master with output TRGO_UPDATE
* the slave timer TIM 1 will get a trigger and run one time
*
* This bit can be set by software, it is automatically cleared by hardware.
* 0: No action
* 1: Reinitialize the counter and generates an update of the registers. Note that the prescaler
* counter is cleared too (anyway the prescaler ratio is not affected). For more see manual. */
TIM2->EGR |= TIM_EGR_UG;
/* Master Configuration */
TIM2->CR2 |= TIM_TRGO_UPDATE;
TIM2->SMCR |= TIM_SMCR_MSM;
/* Enable Counter: */
TIM2->CR1 |= TIM_CR1_CEN;
}Hope you can help me @Community member ��
