STM32 from ground up: NVIC active bit, Processor Modes (FIQ, IRQ, ABT, USR...)

[ilyus]

Context: I'm writing my first STM32 "from the ground up" project. Notepad++ and GCC in command line (Windows 10) are my IDE. I've never done this before, so I'm learning ropes, taking first look into assembly (but keeping own assembly to a minimum, C does the job), writing my first makefile, linker script etc.. I've been working on my NVIC implementation, and I had a few questions I wanted to clarify. Searching the internet gave partial results. I would want to have a full picture from someone who knows the stuff better than I do.

Windows 10, STM32F746 Discovery Board. No CMSIS, no nothing. Mainly C for now. So far, I've created my own vector table, placed .data and .bss where I wanted them to go (SRAM2, because SRAM1 is executable, and who knows if I get cute later and want to run something from SRAM for the fun of it). I successfully run main(void) after reset handler places all data where it's supposed to go.

Question 1: can multiple interrupts be Active at the same time, or is strictly one active at a time, while the other ones are pending? (considering all situations, including low-priority interrupt interrupted mid-execution by higher priority interrupt). I implemented my NVIC function with the assumption that only one interrupt can be active at a time. After that I ran into some material on the internet that may have suggested otherwise. It would be nice to have this question answered once and for all.

Question number 2: while reading programming manual PM0253, I ran into CMSIS functions that generate processor instructions (page 62). The first ones are CPSIE/CPSID. I searched for what they are and ended up on ARM website, which describes what it does and what its parameters are, but gives no context. So I know how to use instruction, but I actually don't know what it does and why would I need it (especially if my program is in C and I can enable or disable interrupts by writing directly to NVIC-related registers, which is can do easily).

So, here is a piece from the ARM website:

My problem with it is the word "abort". Aborting what? I mean, there are 100-ish interrupts on the MCU I'm using, that's clear. But what is Abort? Abort what?

Next, it also mentions some "mode" of processor, so I searched that and ended up on ARM page describing these "modes" that I've never heard of. Not thread and handler mode, but some other modes, which have some weird numbers. Here:

 

As far as I can gather from it, USR mode, which has priviledge level PL0, is basically a thread mode, while PL1 seems like handler mode to me (let's not talk about PL2 for now). Also, as far as I can guess, FIQ means fault handler. Also, my intuitive guess is that different exceptions are associated with different modes (abort mode for memory access exception?). I take it, when I write code in C, the compiler does this mode switching? Or does it happen automatically when exception handler is triggered? What is the point of CPS change processor state instruction? What's the point in manually setting mode to FIQ? And what will happen if I call fault handler while having IRQ mode? They have the same priviledge after all. Oh yes, and I still have no idea what that ABT abort mode is and what it does, it looks like a separate mode that handles memory access exceptions, like MPU-related exceptions. In fact, I failed to find any mention of any of these modes (their abbreviations) in Datasheet/Reference Manual/Programming Manual of my MCU.

I apologise for rather vague question, but I'm trying to learn things here. Your reply could be some text or even just a link to some article or page, where these things are discussed in a friendlier way. Thank you.

[Tesla DeLorean]

The MCU itself has ONE primary IRQ / Interrupt, from the NVIC, support for the peripherals fan-out from there, and the NVIC gets to manage priorities and preemption, etc, and causes the MCU to read different addresses from the vector table. Mix of NVIC+SCB

There's an NMI source, with its vector, and the RESET. You can't mask either of these. I would avoid driving NRST High externally (ie with Push-Pull driver) as this breaks most ARM MCU that expect an Open-Drain implementation, so the MCU can reset via watchdog, or NVIC side. Driven high the MCU won't reset on demand or properly.

The IRQ can be masked via the CPSID / CPSIE, it gates the NVIC's control

Joseph Yiu has an expanding series of Cortex-Mx Essentials type books, these are a different perspective than the TRM/PM docs. Useful if you want to triangulate information from different sources, and different pitches/perspectives.

[ilyus]

Thank you for your reply! I'm already familiar with almost all of this. It's that active bit specifically that I don't know about NVIC. And I have figured out PRIMASK thing too, glad too see I was right about it (found some material online). It's only Active Bit, whose description in the programming manual I found vague (1 bit set at a time or can be multiple). I mean, I guess I could always test it, not that much of a test code anyway.

Does that book talk about modes too? Or where would be the best place to learn how they work? Deeper in ARM docs?

[Pavel A.]

Hi @ilyus​

What exactly do you want to learn and why - to make a product/project or just for amusement?

STM32 family contains "old good" Cortex-M based chips, such as your STM32F746,

Then there are newer Cortex-M23/33 based chips and STM32MP's which are Cortex-A.

Do you want to learn all these or focus on, say, CM7?

ARM documentation indeed may be confusing. ARM is like erupting volcano, they release a lot of stuff every hour. Their v8.1-M "share some features with ARMv8-A",

maybe because of that some Cortex-A terminology and concepts leaked into the CM

documentation.

STM32 programming manuals are based on older ARM documentation, which is relevant for their version of ARM core. ST has also learning resources and code examples.

[ilyus]

Right now I'm playing around with CM7 and CM4, while the intention is to write small RTOS kernel for myself. For the sake of satisfying curiosity, saying that I can, I understand stuff. For future professional prospects. I can totally imagine myself move to some Cortex-A, but not until.I figure this out. Besides, I noticed while different cores obviously have certain differences, after you understand some concept in one place, it's usually the same or similar in idea in other places, so picking up another core type sounds like a matter of adjustment to me (with my limited knowledge).

Anyway, I don't have so much of a general problem, I usually manage to find my answers in the docs eventually. If I get answers to the specific questions I have, I think I will be able to keep moving forward at my pace as I did before.

I think this discussion is going into philosophical direction. I would prefer it stayed focused on NVIC Active Bits and CPS instruction and nothing else. All the other info was merely a context.

[ilyus · Accepted solution]

Meanwhile, I found an answer to my NVIC Active Bit question.

Multiple active bits can be set at the same time. As soon as interrupt handler starts, its active bit is set to 1. Even if this interrupt is interrupted by higher priority interrupt, its active bit will stay 1 until its interrupt handler is done. So if low priority interrupt is interrupted with high priority interrupt, during high priority interrupt hander execution, both handlers will have active bits set to 1.

Source, which explicitly states that: Keil CMSIS documentation active bit function

[Pavel A.]

> I think this discussion is going into philosophical direction.

No, heaven forbid. It's very concrete, NVIC is a Cortex-M thing. Cortex-A has GIC.

ST's Programming Manuals explain the NVIC (these manuals are based on some old good version of the ARM user documents). There also is the classic book by Joseph Yiu.

Keil is ARM; what says Keil - says ARM.

By the way if you've already discovered CMSIS documentation, please read on the __disable_irq , __enable_irq, __get_BASEPRI and related macros. This precisely explains the intent and use of CPS in Cortex-M.