STM 32 SPI COMMUNICATION PROBLEM BTW STM32F407G-DISC1 AND STM32F429I-DISC1 BOARDS

[Moses]

My connection is below:

I have configured STM32F407G as master and STM32F429I as slave from CUBEMX. According to reference manual "The idle state of SCK must correspond to the polarity selected in the SPI_CR1 register (by pulling up SCK if CPOL=1 or pulling down SCK if CPOL=0).", I configured my sck pins as pull down with respect to CPOL=0.

I connected my logic analayzer and MOSI line datas are perfect but MISO line datas are corrupted or another thing. I need a help. I didnot understand what is happening.

[TDK]

Looks okay to me. What is the problem?

Switching noise can affect other signals and manifest as small spikes in the plot. The spikes aren't close to a falling edge, so there is no issue with the SPI signal integrity here.

Capture these in analog mode to get some better insight.

If the problem is the data is incorrect (likely bit shifted left or right), use a CS pin to ensure master/slave are synced up correctly.

[waclawek.jan]

Long wires, improper returns/ground and too high slew rate (GPIO_OSPEEDR setting for MISO/MOSI/SCK) are my suspects #1 in these cases.

JW

[MM..1]

I see primary issue you connect MISO to MISO.

And too good practice is use SS slave select line...

[TDK]

You don't cross MISO and MOSI on an SPI bus. Master Out Slave In.

[MM..1]

Yes sorry my mistake, ofcourse MOSI MOSI is ok, when config on one stm is slave.

[Moses]

I have added chip select or slave select pin from cubemx and I connected to channel 1 of logic analyzer(STM32F407G-DISC1___PB12<-------->STM32F429I-DISC1__PE4). I cannot see any kind of action of slave select pin. When I configure to slave select pin on logic analyzer, logic analyzer cannot show meaningful data on MOSI line. When I do not configure slave select pin on logic analyzer, I have seen data on the picture MOSI line. MISO line still is not good.

If I know truly "HAL_SPI_TransmitReceive(&hspi2, (uint8_t*)aTxBuffer, (uint8_t *)aRxBuffer, BUFFERSIZE, 5000)" using this kind of SPI related command, slave select pin automatically goes to low when transmit begins and goes high when transmit ends.

Do I have any kind of extra thing about slave select pin? Also I do not have analog measurement device to observe spikes of the signal.

[Moses]

Why do you think "too high slew rate " can affect badly on MOSI or MISO lines?

[Moses]

Also my main code for master side(STM32F407G-DISC1) is below. I think code is not wrong.

  /* USER CODE BEGIN WHILE */
  while (1)
  {
//	  HAL_SPI_MspInit(&hspi2);
	  ret = HAL_SPI_TransmitReceive(&hspi2, (uint8_t*)aTxBuffer, (uint8_t *)aRxBuffer, BUFFERSIZE, 5000);
	  switch(ret)
	  {
	  case HAL_OK:
	    /* Communication is completed ____________________________________________*/
	    /* Compare the sent and received buffers */
	    if(Buffercmp((uint8_t*)aTxBuffer, (uint8_t*)aRxBuffer, BUFFERSIZE))
	    {
	      /* Transfer error in transmission process */
	      HAL_GPIO_WritePin(GPIOD, LD5_Pin, SET);
//	      while(1);
	    }
 
	    /* Turn LED4 on: Transfer in transmission process is correct */
	    HAL_GPIO_WritePin(GPIOD, LD4_Pin, SET);
	    /* Turn LED6 on: Transfer in reception process is correct */
	    HAL_GPIO_WritePin(GPIOD, LD6_Pin, SET);
	    break;
 
	  case HAL_TIMEOUT:
	    /* A Timeout occurred_____________________________________________________*/
	    /* Call Timeout Handler */
	    HAL_GPIO_WritePin(GPIOD, LD5_Pin, SET);
		HAL_Delay(500);
	    HAL_GPIO_WritePin(GPIOD, LD5_Pin, RESET);
		HAL_Delay(500);
	    break;
 
	    /* An Error occurred______________________________________________________*/
	  case HAL_ERROR:
	    /* Call Timeout Handler */
	    HAL_GPIO_WritePin(GPIOD, LD5_Pin, SET);
	    break;
 
	  default:
	    break;
	  }
 
	  HAL_Delay(2000);
 
    /* USER CODE END WHILE */

[waclawek.jan]

You still did not tell us, why do you think your SPI communication is failing. What exactly are the symptoms and how are they different from the expectations?

> Why do you think "too high slew rate " can affect badly on MOSI or MISO lines?

It introduces high-frequency content which can affect either the other line through radiated interference, or through improper/common return/ground. That's the glitches you see and don't want to see. As TDK said above, those glitches are not detrimental to data transfer themselves, as data are sampled on the opposite edge of SCK than shifted out.

Too high slew rate on SCK is another story, as it can introduce spurious glitches which can act as false extraneous SCK edge/pulse, leading to data corruption.

> I cannot see any kind of action of slave select pin.

On master, set the pin as GPIO Output and toggle it "manually".

JW