SPI Configuration (bare metal-stm32h743)

[NBlac]

I am trying to code the stm32h743 for spi communication and i can't seem to transmit. I am using PA5 as SCK and PD7 as MOSI. I read the procedure required that is in the reference manual (49.4.9 https://www.st.com/resource/en/reference_manual/dm00314099.pdf ) and wrote the code below but it doesn't transmit 0x3 (checked with oscilloscope).

RCC->AHB4ENR |= RCC_AHB4ENR_GPIOAEN;   // clock enable for gpio A,B,D
RCC->AHB4ENR |= RCC_AHB4ENR_GPIODEN;          
RCC->AHB4ENR |= RCC_AHB4ENR_GPIOBEN;
RCC->APB2ENR |= RCC_APB2ENR_SPI1EN;   // enable SPI clock
 
GPIOA->MODER &= ~GPIO_MODER_MODER5;   // enable alternate functions for gpioa and d
GPIOA->MODER |= GPIO_MODER_MODER5_1;  // 0b10 for alternate function, (PIN5)
GPIOA->AFR[0] |= (0x05 << 5 * 4);      //  AF5 for SPI which is 0101 (it's a 4bit variation)
 
GPIOA->MODER &= ~GPIO_MODER_MODER6;  // PIN6
GPIOA->MODER |= GPIO_MODER_MODER6_1;
GPIOA->AFR[0] |= (0x05 << 6 * 4);
 
GPIOD->MODER &= ~GPIO_MODER_MODER7;  // PIN7
GPIOD->MODER |= GPIO_MODER_MODER7_1;
GPIOD->AFR[0] |= (0x05 << 7 * 4);
 
SPI1->CFG1=(7u << SPI_CFG1_DSIZE_Pos);  // 8bit data size
SPI1->CFG2|=SPI_CFG2_MASTER ;  // master mode
SPI1->CR1|=SPI_CR1_SPE;           // spi enable
SPI1->CR1|=SPI_CR1_CSTART;        // transfer start
*(volatile uint8_t *)&SPI1->TXDR = 0x3;

I checked with the debugger and all the settings are configured correctly to all the registers up until the last two lines where i don't see any change and can't transmit anything. Master mode (line 19) also doesn't configure, register stays 0. And transfer start bit can't change to 1 if master mode is not enabled.

Any ideas? Also, am i missing any other settings for SPI configuration?

thanks

[Tesla DeLorean]

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[Andreas Bolsch]

Hm, looking at Fig. 608 and text below I'd check whether spi_ker_ck is activated.

[NBlac]

The only thing i could find in the reference manual is this: https://imgur.com/a/vg17TPC

(Sorry, the image button doesn't seem to work on my browser)

Where the kernel clock is selected.

[waclawek.jan]

I don't use the H7 and looking at the RM the SPI module has undergone some serious rework, so maybe it's not the case here, but:

> Master mode (line 19) also doesn't configure, register stays 0.

in the "older" SPIs resulted from NSS (in 'H7 apparently renamed to SS, for some extra confusion to those attempting to migrate) being low (which it is if it's not configured to any pin nor as internal, a nice undocumented feature) forcing SPI into slave mode. You should see this in the status registers MODF bit being set immediately after the attempt to set the master bit.

If you don't intend to use the hardware (N)SS pin, you ought to set both SSM and SSI (see footnote under Master and three independent slaves at star topology figure).

JW

[NBlac]

I'll be using software SS so i set ( like you said) SSM, SSI and SSOE and now master mode is enabled along with spi_enable and transfer_start.:grinning_face:

However, the data register (TXDR) doesn't store the 0x3 value.

[waclawek.jan]

It's a write-only register.

[NBlac]

Oh, ok. I still however don't see anything being transmitted with an oscilloscope.