SPi communication in stm32f407vgtx board

[Ash1]

Hi all

I am working with SPI1 on stm32f407vgtx and issue what I am, facing my NSS which internally controlled by SPI is taking more time for goes high even CLOCk has been stopped . my configuration are SPI full duplex 16 bit data clock is 2.6MHZ after prescaled I am transmitting on spi every 10ms task. Please check the screenshot of logic analyzer for further understanding .

Note: in the end I have disabled SPE bit  before checking TXE and busy flags.

[TDK]

NSS remaining low is not a problem for the SPI protocol. On the STM32F4, NSS will remain low as long as the SPI peripheral is enabled. I recommend using a GPIO pin for the CS pin.

[Ash1]

Hi

I have a observed that every times after 4th CLOCK 5th clock is taking twice than rest.

why it happening please check the image.

[TDK]

This is a sampling rate issue. Increase the sampling rate on the logic analyzer and/or slow down the SPI clock speed if this bothers you.

[Ash1]

Hi 

What about the clock ..I want to know when I will start seeing clock and when it goes off, who actually controls the clock .

B.R

Ash

[Ash1]

hi stm32' community

I am sharing you zip of my project can you check my spi code is it correct on logic analyzer or anywhere.

I request you to help me to achieve SPI communication.

I am sharing screenshot you can clearly in the end you may notice a time gap how late cs goes high even when I have disabled cs immediately after reading SPI_dr register.

[Ash1]

Hi

I am waiting for your response .

B.R

Ash

[TDK]

> HAL_SPI_Transmit(&hspi1, TX_Buffer, 1, 1000);

This is the only SPI-related statement in your code. I don't see manipulation of CS anywhere or disabling the SPI peripheral anywhere.

Still stand by my first statement. NSS will be low as long as the peripheral is enabled. Better to use a GPIO pin here.

[Andrew Neil]

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@Ash1 wrote:

who actually controls the clock .

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By definition, it is the Master which controls the clock in SPI.

[Andrew Neil]

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@TDK wrote:

Still stand by my first statement. NSS will be low as long as the peripheral is enabled. .

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Indeed - that is the defined behaviour:

https://www.st.com/resource/en/reference_manual/rm0090-stm32f405415-stm32f407417-stm32f427437-and-stm32f429439-advanced-armbased-32bit-mcus-stmicroelectronics.pdf#page=880

via: https://www.st.com/en/microcontrollers-microprocessors/stm32f407vg.html#documentation