SPi communication in stm32f407vgtx board

[Ash1]

Hi all

I am working with SPI1 on stm32f407vgtx and issue what I am, facing my NSS which internally controlled by SPI is taking more time for goes high even CLOCk has been stopped . my configuration are SPI full duplex 16 bit data clock is 2.6MHZ after prescaled I am transmitting on spi every 10ms task. Please check the screenshot of logic analyzer for further understanding .

Note: in the end I have disabled SPE bit  before checking TXE and busy flags.

[TDK]

NSS remaining low is not a problem for the SPI protocol. On the STM32F4, NSS will remain low as long as the SPI peripheral is enabled. I recommend using a GPIO pin for the CS pin.

[Ash1]

Hi

I have a observed that every times after 4th CLOCK 5th clock is taking twice than rest.

why it happening please check the image.

[TDK]

This is a sampling rate issue. Increase the sampling rate on the logic analyzer and/or slow down the SPI clock speed if this bothers you.