Speculation on STM32F767

GGran.2 · ‎2024-10-07

Hello,

I'm studying the STM32F767 MCU, and I noticed that in STMCubeIDE is possible to configure if the speculation is permitted, but I didn't find an explanation of this feature. If I set Speculation disabled, do I set the flash strongly-ordered? Does speculation concern only the flash or it concerns also the other memories?

Thank you

SofLit · ‎2024-10-08

Hello @GGran.2 ,

Indeed the speculation could also be performed to the internal memories but the impact is very negligible as the access is 1 cycle.

If the CPU does a speculation for a non-initialized memory i.e. the default timing of the memory interface keeps the worst/larger latency, It will impact the application performance without any added value as the speculation and the fetch is not used later and discarded by the CPU. For example for the case of FMC, if the interface is not configured the default timing is the worst case with 0xFF values in the timing registers leading to a very high latencies when the CPU speculates to the FMC memory. We can see this behavior by an LCD flickering. Note that if an external memory is used, the speculation is there but with less impact because the memory timing is configured by the user and will not for sure having the same impact as non-initialized memories.

To conclude, the speculation on Cortex-M7 is there to enhance the performance. If the result of the speculation is taken, we gain in the performance, if rejected, no impact if the speculation is performed on the internal memory but it could be some impact when it is performed on an external memory.

You can also refer to the AN4861 "Introduction to LCD-TFT display controller (LTDC) on STM32 MCUs" / Section 5.6 Special recommendations for Cortex-M7 (STM32F7/H7).

Hope I answered your question.

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SofLit · ‎2024-10-07

Hello,

In CubeMx while you start a new project with a Cortex-M7 based microcontroller, it invites you to disable the speculative access using background MPU configuration.

This setting is to prevent the speculative access to unused external memory regions such as FMC, QSPI etc ..

Internal memories including the flash are not impacted by the speculation.

For more explanation, please refer to this thread.

Hope I answered your question.

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GGran.2 · ‎2024-10-07

Thank you for the answer, but I didn't understand if the disabling of the speculation set the external memories to device (or strongly ordered). Is the disabling the same of setting the MPU? And why the internal memories are not impacted by the speculation?

Thanks

SofLit · ‎2024-10-08

Hello @GGran.2 ,

Indeed the speculation could also be performed to the internal memories but the impact is very negligible as the access is 1 cycle.

If the CPU does a speculation for a non-initialized memory i.e. the default timing of the memory interface keeps the worst/larger latency, It will impact the application performance without any added value as the speculation and the fetch is not used later and discarded by the CPU. For example for the case of FMC, if the interface is not configured the default timing is the worst case with 0xFF values in the timing registers leading to a very high latencies when the CPU speculates to the FMC memory. We can see this behavior by an LCD flickering. Note that if an external memory is used, the speculation is there but with less impact because the memory timing is configured by the user and will not for sure having the same impact as non-initialized memories.

To conclude, the speculation on Cortex-M7 is there to enhance the performance. If the result of the speculation is taken, we gain in the performance, if rejected, no impact if the speculation is performed on the internal memory but it could be some impact when it is performed on an external memory.

You can also refer to the AN4861 "Introduction to LCD-TFT display controller (LTDC) on STM32 MCUs" / Section 5.6 Special recommendations for Cortex-M7 (STM32F7/H7).

Hope I answered your question.

To give better visibility on the answered topics, please click on "Accept as Solution" on the reply which solved your issue or answered your question.

Tesla DeLorean · ‎2024-10-08

>>And why the internal memories are not impacted by the speculation?

Likely because reading them twice has no consequence.

More longer term interactions, across buses, especially to things like FIFO's / peripheral registers, has repercussions

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GGran.2 · ‎2024-10-09

You are kind, but I probably need to study better how speculation works, because I didn't understand anything. The problem is that I can't find any documentation that explains it.

SofLit · ‎2024-10-09

Unfortunately ARM doesn't disclose more information about it.

See this link from ARM: https://developer.arm.com/documentation/ddi0489/f/memory-system/speculative-accesses/considerations-for-system-design

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