The Reference Manual for at least some of the F4 series talks about a specific ratio, which I interpret to prevent clock inversions or pipeline stalls as it moves data across clock domains.
"PCLK2 and SDIO_CK clock frequencies must respect the following condition: Frequency(PCLK2) ≥ 3 �?� 8 × Frequency(SDIO_CK)"
On the original F4 there wasn't an explicit statement about the PLL running, so there was some confusion about why a 16 MHz HSI run system couldn't use SDIO. In the days of CubeMX diagrams this is perhaps a little clearer, plus in later model F4's the "48 MHz" source could be derived elsewhere and could be higher..
"The SDIO uses two clock signals:
• SDIO adapter clock SDIOCLK up to 50 MHz (48 MHz when in use with USB)
• APB2 bus clock (PCLK2)"
It doesn't explicitly state this comes from a PLL that must be running, and a work-around for an errata puts the top speed at 75 MHz, not 50 MHz. The same errata for the older model F4 indicates BYPASS mode doesn't work properly, and experience indicates HW Flow Control is also broken.
Polled mode has some vulnerabilities to overrun/underrun, as the data transfer phase is not interruptable, and is intolerant to the MCU wandering off to other tasks mid-stream.
2 MHz in my estimation is very slow, a properly wired and terminated SD cards should get to 24 MHz without a problem. There are checks for signal slew in 4-bit mode, but I don't think those present as over/under-run conditions.
