CubeMX represents a finite universe of choices, the hardware can do more, but there is perhaps not boiler-plate code to manifest an end-to-end solution at the press of a button.
I don't recall if any given part has a NAND READY/NWAIT pin, or how much of the bus is exported. You'd need to walk the Reference Manual and Data Sheet to double check.
Parallel NAND flash needs a handful of Address bits, and 8 or 16-bit Data bits depending on the devices chosen. Some read/write lines, and a chip-select. Then a lot of software to manage, buffer, and deblock the large NAND sectors, and also handle the wear-leveling and ECC. Requirements are probably closest to that of an LCD.
Parallel NAND Flash is a bit of an evolutionary dead-end, most people needing mass storage are using eMMC, or looking at QSPI NAND Flash in lower densities (1Gb)
