SAI / I2S w/ multiple sampling rates & Audio Clock Input (I2S_CKIN)

[LCE]

In all the STM32s that have I2S / SAIs and ethernet that I've checked, there is this fixed oversampling ratio of 256 between master clock and sampling rate.

When using the internal PLL to get the sampling clocks, no problem (amazing how good and stable these clocks are, even with the 8 MHz from the STLink, checked it with generating 24bit/192k SPDIF signals).

But in my case I must use the extra "Audio Clock Input (I2S_CKIN)", which does not have the benefit of getting modified by a PLL.

So my problem now: how do I get 3 different sampling rates (e.g. 48k / 96k / 192k) without dividing the clock (done that, but no space available) outside of the STM32 ?

And without any downsampling by the CPU.

Any ideas? Something I have overseen?

[waclawek.jan · Accepted solution]

 

JW

[LCE]

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Wow, really that simple?!

Thanks again!

I will try that tomorrow.

This part from the F4 / F7 ref manuals somehow made me think it would work only when the clock comes from an internal PLL or if TDM is used:

"The clock source for the clock generator comes from the product clock controller. The

sai_x_ker_ck clock is equivalent to the master clock which can be divided for the external

decoders using bit MCKDIV[3:0]:

MCLK_x = sai_x_ker_ck / (MCKDIV[3:0] * 2), if MCKDIV[3:0] is not equal to 0000.

MCLK_x = sai_x_ker_ck, if MCKDIV[3:0] is equal to 0000.

MCLK_x signal is used only in TDM."

So what actually does this last TDM restriction mean?

[waclawek.jan]

In the 'F446 RM I've quoted from, this sentence referes - more correctly - to Free mode.

Even then IMO it's bogus, and they just wanted to say in a cumbersome manner that for SPDIF-Tx and AC97 you don't need to generate MCLK signal.

JW

[LCE]

Just checked it, and as now expected, it works!

I should have just tried...

Thanks!