When writing to FMC NAND address, FMC_NCE goes low at beginning of first write and then only comes high at end of last write. I can write 0x1000 words at 10MHz using a 60MHz FMC kernel clock. Therefore with the minimum SETUP, WAIT, and HOLD time, it takes 6 kernel clocks to write out a word.
When reading, FMC_NCE goes low and then high with every word read. This increases the read time between each word, requiring extra FMC kernel clock cycles, which means running the kernel clock at a higher rate. The higher kernel clock has the added detriment of being inconsistent number of clock cycles between reads. At 160MHz FMC kernel clock, the read sometimes takes 16 clocks, or 15, or 17.
I'm not actually writing to a NAND memory chip, so I need to be consistent with the read frequency in particular.
The WRITE code:
for (index = 0U; index < BUFFER_SIZE; index++)
{
*(__IO uint16_t *)deviceAddress = *buff;
buff++;
}
The READ code:
for (index = 0U; index < BUFFER_SIZE; index++)
{
*buff = *(__IO uint16_t *)(deviceAddress);
buff++;
}
Somehow, the peripheral knows the write is all in one go, but the read isn't?
I have set the MPU to TEX2 and have i- and d-cache enabled.
I would really appreciate any ideas
