Hi,
I am trying and failing to work out a stable transmission between STM32H743 and a MT29F64G08CBABBWP-12IT:B TR MLC 64Gbit NAND chip.
95%+ of the time transmission works as intended (write -> read -> verify cycle passes) but when it fails, it's random on what block / page it happens so I think we can rule out bad blocks being the root cause. I have tried everything I can think of - from changing the configured timings one by one to swapping out the ECC library I use and the results still stay the same.
Any hints would be greatly appreciated.
I have disabled DCache and MPU. NAND is sharing the FMC data bus with SDRAM which is configured, but no access is being performed to the SDRAM when performing NAND tests.
Transmission is done by DMA (MDMA with 4 channels used, each respectively for page RX, page TX, spare page RX, spare page TX). FMC is clocked from PLL2R set to 240MHz.
Currently i have NAND set to mode 0 (10MHz) with the relevant timings being:
- tCLS: 50ns
- tCS: 70ns
- tALS: 50ns
- tCLR: 25ns
- tAR: 25ns
- tWP: 50ns
- tRP: 50ns
- tCH: 20ns
- tCLH: 20ns
- tALH: 20ns
- tDS: 40ns
- tREA: 40ns
and configured timings / parameters being:
hnand1.Init.NandBank = FMC_NAND_BANK3;
hnand1.Init.Waitfeature = FMC_NAND_WAIT_FEATURE_ENABLE;
hnand1.Init.MemoryDataWidth = FMC_NAND_MEM_BUS_WIDTH_8;
hnand1.Init.EccComputation = FMC_NAND_ECC_DISABLE;
hnand1.Init.ECCPageSize = FMC_NAND_ECC_PAGE_SIZE_256BYTE;
hnand1.Init.TCLRSetupTime = 5;
hnand1.Init.TARSetupTime = 6;
/* hnand1.Config */
hnand1.Config.PageSize = 8192;
hnand1.Config.SpareAreaSize = 744;
hnand1.Config.BlockSize = 256;
hnand1.Config.BlockNbr = 4096;
hnand1.Config.PlaneNbr = 2;
hnand1.Config.PlaneSize = 2048;
hnand1.Config.ExtraCommandEnable = DISABLE;
/* ComSpaceTiming */
ComSpaceTiming.SetupTime = 4;
ComSpaceTiming.WaitSetupTime = 11;
ComSpaceTiming.HoldSetupTime = 5;
ComSpaceTiming.HiZSetupTime = 10;
/* AttSpaceTiming */
AttSpaceTiming.SetupTime = 4;
AttSpaceTiming.WaitSetupTime = 11;
AttSpaceTiming.HoldSetupTime = 5;
AttSpaceTiming.HiZSetupTime = 10;
This chip requires 40-bit ECC per 1117 bytes of data so I'm currently using BCH ECC set to 4-bit correctability per 256B chunk. which gives 48 bits of ECC per chunk.
The library I use currently is an adapted version of the BCC code found in the Linux kernel so it should be tested enough.
I store 2 copies of the ECC data and 4 copies of ECC CRC per chunk and I haven't yet observed an instance when no valid ECC could be found (at most it would work after a Read Retry cycle) but sometimes I do observe an instance where after (apparently) successful ECC correction the data is still invalid.
I can post code snippets or any additional info if required.
Again, any help is greatly appreciated.
