Questions about Clock Synchronization for LPTIM1 on L4xxx Series

[AMacd.1]

The Reference Manual for L4 series (RM0394) says on page 1007:

"When the LPTIM is running with an asynchronous clock, reading the LPTIM_CNT register may
return unreliable values. So in this case it is necessary to perform two consecutive read accesses and verify that the two returned values are identical.
It should be noted that for a reliable LPTIM_CNT register read access, two consecutive read accesses must be performed and compared. A read access can be considered reliable when the values of the two consecutive read accesses are equal."

1. What does "asynchronous clock" mean?

2. The block diagram, Figure 337 on page 988 shows a "Synchronization" block but is vague as to what this pertains to.

3. Also, what is meant by "kernel clock"?  If I am using the LSI oscillator for the clock source (CLKMUX = 0), where does this "lptim_ker_ck" come from?  How is this mapped to LSI clock?  This is confusing.

4. If the LPTIM1 is being fed by LSI clock, does the caveat page 1007 still apply?

5. The HAL driver obtains the counter value without performing multple reads until 2 consective reads match:

/**
  * @brief  Return the current counter value.
  * @PAram  hlptim LPTIM handle
  * @retval Counter value.
  */
uint32_t HAL_LPTIM_ReadCounter(const LPTIM_HandleTypeDef *hlptim)
{
  /* Check the parameters */
  assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));

  return (hlptim->Instance->CNT);
}

So why does the HAL implementation ignore the advice in the reference manual?

[Bob S · Accepted solution]

In this case, an asynchronous clock is any clock that is "unrelated" to the APB clock.  The LSI and LSE clocks are  always asynch to the HSI, HSE and MSI clocks (and the derived APB/AHB clocks).  In your case, since you are using the LSI as the clock source for the LPTIM, that means it is running asynchronously to the rest of the chip (SYSCLK/APB/AHB clocks).

The "synchronization" block in the diagram makes it possible for the LPTIM register interface to read the counter that is clocked by a different/async clock.  If you were to sample the counter on a single APB clock edge (async to the timer's clock), you could read the data as it is changing, so you get some "new" bits and some "old" bits.  The synchronizer makes sure the data is stable in the APB clock domain.

The LPTIM kernel clock is is whatever clock is routed to the LPTIM block from the RCC (HSI, LSI, LSE or APB clock).  That would be LSI in your case.

Yes, the caveat applies.  You either need to call the HAL function 2 times or write your own "read counter" function.

[AMacd.1]

Thanks @Bob S. That is a clear and concise answer and it is greatly appreciated!.