The Reference Manual for L4 series (RM0394) says on page 1007:
"When the LPTIM is running with an asynchronous clock, reading the LPTIM_CNT register may
return unreliable values. So in this case it is necessary to perform two consecutive read accesses and verify that the two returned values are identical.
It should be noted that for a reliable LPTIM_CNT register read access, two consecutive read accesses must be performed and compared. A read access can be considered reliable when the values of the two consecutive read accesses are equal."
1. What does "asynchronous clock" mean?
2. The block diagram, Figure 337 on page 988 shows a "Synchronization" block but is vague as to what this pertains to.
3. Also, what is meant by "kernel clock"? If I am using the LSI oscillator for the clock source (CLKMUX = 0), where does this "lptim_ker_ck" come from? How is this mapped to LSI clock? This is confusing.
4. If the LPTIM1 is being fed by LSI clock, does the caveat page 1007 still apply?
5. The HAL driver obtains the counter value without performing multple reads until 2 consective reads match:
/**
* @brief Return the current counter value.
* @PAram hlptim LPTIM handle
* @retval Counter value.
*/
uint32_t HAL_LPTIM_ReadCounter(const LPTIM_HandleTypeDef *hlptim)
{
/* Check the parameters */
assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
return (hlptim->Instance->CNT);
}
So why does the HAL implementation ignore the advice in the reference manual?
