Hello all,
I am working with the STM32WB series and using a 32 MHz crystal for the HSE (specifically the Murata XRCGB32M000F1SBBR0 on my custom board).
To verify correct operation, I measured the analog waveform on OSC_IN and OSC_OUT using a low-capacitance active probe (Keysight N2796A).
Observation
On both my custom board and the official NUCLEO-WB55 evaluation board, I consistently measure the following:
OSC_OUT ≈ 500 mVpp, ~400 mV DC bias
OSC_IN ≈ slightly lower amplitude but similar bias (~400 mV)
The two boards produce almost identical results, so this does not appear to be a layout or crystal-selection issue on my side.
Documentation gap
I cannot find any ST document (datasheet, reference manual, AN2867, or app notes specific to STM32WB) that specifies:
Expected voltage swing amplitude on OSC_IN or OSC_OUT
Expected bias point
Typical or minimum oscillator drive level in terms of Vpp for HSE on the STM32WB series
The datasheet provides the crystal requirements (ESR, CL, drive level, etc.), but there is no numeric information describing the analog signal level at the HSE pins.
Request
Can ST please confirm whether the following measurements are correct / expected for the STM32WB series?
OSC_OUT ≈ 500 mVp-p on ~400 mV DC bias
OSC_IN ≈ slightly lower Vpp, similar bias
Since the EVM and my custom board show the same waveform, I want to verify with ST whether this amplitude level is considered valid for proper crystal oscillation on STM32WB.
Summary of questions
Does ST have an official or internal expected Vpp range for HSE on STM32WB?
Is ~500 mVp-p with ~400 mV bias within the correct operating range for the HSE oscillator?
If not, what amplitude should be expected or checked during validation?
Thank you.
Nir
