Hi @Oliver Müller
I don't understand how ST do this. But here is my take on things:
Memories are big - they occupy a fairly large area of silicon.
It is likely that some of the transistors used to make a memory come out faulty - perhaps due to a speck of dust.
In order to improve the proportion of chips that can be sold, chip manufacturers will actually make more blocks of memory than they say are in the chip. And they have some way to record "this block is faulty - when you want to access it, actually use that spare block".
I assume the "higher endurance" blocks are simply ST making use of some of these spare blocks. It could be done dynamically - they keep a count of erase cycles for each block. And then when one block hits 10k cycles it is paired-up with a "spare" block so that both blocks are written/read at the same time. (Quite what this does to power-consumption I'm not sure). But having two memory cells for each bit (and error-correction-coding bits) greatly decreases the likelihood of wear making a memory location read the wrong value. So they can (statistically) offer a much better lifetime.
Precisely how ST do this will be covered by Patents and trade-secrets. I don't expect ST to be too open about how it works.
