QUAD SPI External Memory Performance STM32

[AlanM]

Hi There - I'm very new to electronic design and need help making a key design decision. Specifically I want to know that the performance will not be a problem when writing to external memory from a stm32 over Quad Spi. I don't want to end up making a school boy error whereby the memory bus or memory chip cannot accomodate the rate at which I want to write data - or maybe there is another practical reason I am unaware of.

Quite simply I want to poll a magnetic position encoder and an accellerometer at circa 200Hz over the regular spi bus and then write their values to the flash memory on the Quad spi bus for analysis later. This is essentially the data logger part of the application. Probably worth mentioning that we are doing some other data analysis on the data as the sensors are polled so some overhead there for the M4 processor - but an existing application uses an M0 processor at 16Mhz and does this analysis fine so we reckon that the M4 at 64Mhz should easily cope.

Really before proceeding I am looking for an indication that I am going to be able to write a timestamp and two sensor values to the external memory at 200Hz - possibly even higher - and it will just work as expected. 

Feedback gratefully received

[Rainer1]

Hello,

this mainly depends on two (or three) factors

1. Your MCU's QSPI maximum speed specification from the "electrical characteristics" in the MCU's user user manual. The minimum required QSPI clock frequency depends on the number of bytes+overhead you want to write with 200Hz, but sounds manageable via QuadSpi for an M4 @ 64 MHz.
2. The maximum Byte or Page write time from the QuadSpi memories reference manual: This depends very much from the external storage technology. Could be critical at your planned write load with flash/eeprom, but no problem with fram.
3. The PCB design and also supply voltage could also be a limiting factor for QuadSpi speed, but unlikely for your requirements.

[waclawek.jan]

There are devboards (some of the Disco) with QSPI FLASH onboard, so you can write easily try yourself.

JW

[Tesla DeLorean]

NOR Flash is very slow for erase/write.

For IC level data logging applications use eMMC, which is basically a soldered down SD Card

[AlanM]

Thank you everybody for your feedback. I have a further question based on your answers.

Simply - how much faster would an eMMC/SDIO solution be than Flash/QSPI in terms of data rates?

AM

[Rainer1]

Let's assume a QSPI clk of 80MHz, then yo will have a maximum data rate of 80MB/s in QSPI double data rate mode. In eMMC HS400 mode, which implies 1.8V IO level, 8 data lines and DDR, the maximum data rate will be 400MB/s @ 200MHz clk.

But, independent from technology, the write performance is far below these theoretical values. You will have to check out the write performance from the datasheet and implement a proper buffer & write strategy.

[berendi]

> I am looking for an indication that I am going to be able to write a timestamp and two sensor values to the external memory at 200Hz - possibly even higher

Data transfer rates are (almost) meaningless. It might not even be possible to slow down the STM32 SPI interface so much that you could not transmit maybe 96 bits of data in 5 ms, including command overhead.

Assuming 96 bits (12 bytes) of payload and 64 bits (8 bytes) of overhead, there are still only 32000 bits to transmit in a second. Increasing the sampling rate tenfold, i.e. 2 kHz, we are at 320 kbit/s, i.e. 1/1000th of the capacity of a 80 MHz quad spi interface.

Unless you are an experienced electronic designer, you do not want to deal with the implications of 80 MHz signals in your system. I would rather calculate with 1 MHz to avoid EMI issues. It would still be more than enough for the amount of data you are going to deal with. Even a conventional SPI connection would comfortably handle it at 1 MHz.

More important is the time it takes to erase and write a block of flash memory. While SD/eMMC datasheets suggest impressive data rates, they are average values. I am yet to see an SD/eMMC datasheet which guarantees that writing a 512 bytes block would never take more than X ms. Its wear leveling logic might decide any time that it just needs some 50 or 150 ms to shuffle around some blocks internally. Although I am reasonably sure that buffering one second worth of data would be enough to compensate for this.

On the other hand, SPI NOR flash datasheets tend to be clear on the topic. The one I happen to be using (W25Q128JV-DTR) guarantees that writing a 256 byte page would take no more than 3 ms (4k in 48 ms, 64 k in 768 ms), erasing 4 kbyte would take no more than 400 ms and erasing 64 kbyte would take at most 2000 ms. You would need somewhat larger buffers, or maybe connect two SPI flashes to write one while the other is being erased.

Furthermore, you should look at the price tag attached to them, if you do not need to store gigabytes, then you might not need a $5 eMMC, but a $0.5 SPI NOR flash. Consider the packaging, are you ready to mount BGA parts? And programming SPI is much simpler than working with the SD/MMC interface.

[waclawek.jan]

...and maybe erase won't need to be performed "on the fly"... that depends on the particular application of course.

And depending on data amount, you might want to look also at FRAMs and perhaps serial SRAMs.

JW