Let's assume a QSPI clk of 80MHz, then yo will have a maximum data rate of 80MB/s in QSPI double data rate mode. In eMMC HS400 mode, which implies 1.8V IO level, 8 data lines and DDR, the maximum data rate will be 400MB/s @ 200MHz clk.But, independen...

Hello,this mainly depends on two (or three) factorsYour MCU's QSPI maximum speed specification from the "electrical characteristics" in the MCU's user user manual. The minimum required QSPI clock frequency depends on the number of bytes+overhead you...

Here are two of the example projects dealing with shared memory:https://github.com/STMicroelectronics/STM32CubeH7/tree/master/Projects/NUCLEO-H745ZI-Q/Applications/FreeRTOS

There are several examples in the STM32H7 Cube FW in the H745 folders, where this scenario is used.In general: Place the shared variables in a SRAM region accessible by both cores, i.e. SRAM1 - 4guarantee cache integrity for the CM7, the easiest way ...