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Problem with ST SPI on STM32L475.

KPerg.1
Associate II

Hello,

I am using STM32L475 board and trying to communicate with VNF1048F by SPI. The communication protocol which is used is defined as ST-SPI.
_legacyfs_online_stmicro_images_0693W00000bhx83QAA.png On STM32 I can configure at maximum 16 bit communication but the device (VNF1048F) requires 32-bit frames. That is why I am using 8 * 4 bit. On regular basis I spi error bit is getting set, but only when reading certain registers.


_legacyfs_online_stmicro_images_0693W00000bhx1KQAQ.pngCurrently, on each signal line, there is current limiting resistor 3 Ohm. Here marked in red are the errors - 0x21 means SPIE and FAIL_SAFE is set. It happens always on the same registers 0x11, 0x14, 0x16, and 0x17. I have completely no idea what can be a source of a problem. I will be more than happy if you could have any helpful suggestions.


_legacyfs_online_stmicro_images_0693W00000bhx9VQAQ.png

3 REPLIES 3
S.Ma
Principal

If this SPI has 32 bit HW FIFO, I would suggest to use SPI in 8 bit mode.

You can write 8, 16 or 32 bit, they will be sliced in 8 bit serial chunks.

The write to DR will determine the number of SCK clock bits.

TXE is only used to push out data and clocks

RXNE is used to know when the transmission is completed to the last bit. This one should be the prime interrupt source if sending (and receiving simultaneously) data blocks.

I am doing as you suggested using 8 bit mode. Currently, I am using the HAL library for transfer as can be seen below:


_legacyfs_online_stmicro_images_0693W00000bhxjOQAQ.png

KPerg.1
Associate II

Also maybe anyone know what CSN low timeout does mean?
_legacyfs_online_stmicro_images_0693W00000bhxn6QAA.png