Hello ST Community and Support Team,
I try to play with Independant Watchdog and Window Watchdog on a Nucleo U575ZI eval board.
I was able to configure counters, window and even EWI interrupt perfectly thanks to STM32 HAL library watchdog related functions and see a reset when timeout is too low and no reset when the refeeding is done on time.
==> I have now problems setting the correct value to have the expected timeout of around 2 seconds I want.
1) On WWDG, the prescaler schematic is pretty clear and with ST example code with counter = 0x7F and prescaler 64, we expect to have around 209,71ms of timeout with the following formulas :
WWDG Counter Clock = PCLK1 / (4096 * Prescaler)
WWDG Counter Time (ms) = 1000 / WWDG counter clock
WDG Timeout (ms) = Counter settings * Counter Time
So theorically, with PCLK1 = 160MHz, we can reach only around 419ms maximum when using PRESCALER 128 and Counter 0x7f right ?
When doing some experiment on my board with this last settings, I have only decreased of around 8 counter ticks (so not generating a reset as we reach 0x77) in 500ms in Debug mode, can you explain how ? My project was generated with CubeMX so PCLK was set to 160MHz...
2) On IWDG, all work correctly and seems to be good to reach the 2 seconds target, it is just the using the following formula I cannot get the exact same result as what is shown in ST example test (Counter = 1561 (in decimal), PRESCALER 16, by calculus : 780 ms whereas ST example claims for 736ms....)
IWDG Clock= LSI / Prescaler
IWDG Counter Time (ms) = 1000 / IWDG clock
IWDG Timeout (ms) = Counter * Counter Time
LSI clock is 24KHz as I not enable the /128 Prescaler before IWDG.
=> Can you point me where I do wrong in my formula ?
Nice regards,
