cancel
Showing results for 
Search instead for 
Did you mean: 

NVIC IABR - Information about what interrupt is active cant be found

Tobe
Senior III

Where can i get the information about which interrupt is activated for each of those bits? How can such information be so hard to find? Cant find it on the ARM website! Just the information, that it shows activated interrupts, which is essentially useless... *facepalm*

1 ACCEPTED SOLUTION

Accepted Solutions

Easier to get this information from the VECTACTIVE field in SCB->ICSR.

LSB of IABR0 corresponds to "NVIC position" 0 which is WWDG1 here. Goes up from there, 32 per register.

13 of them don't have "NVIC position" values because they're system interrupts and not reported anywhere in IABR.

If you feel a post has answered your question, please click "Accept as Solution".

View solution in original post

8 REPLIES 8
TDK
Guru

Interrupts past the first 16 are vendor-defined. They are the in the reference manual of the relevant chip. For example:

TDK_0-1726771357865.png

 

If you feel a post has answered your question, please click "Accept as Solution".

I see 13 without a NVIC position. I still dont know which bit corresponds to which interrupt.

Enumerate the entire table..

Architecturally:

256 bits on IABR [0..7]

16 System Handler

240 IRQHandlers (assigned by implementer, so STMicro for STM32's)

16 + 240 = 256

Divider the Address in Vector Table by 4

Check IABR0.15 is asserted whilst in SysTick_Handler

Check IABR0.26 is asserted whilst in EXTI4_IRQHandler

Tips, Buy me a coffee, or three.. PayPal Venmo
Up vote any posts that you find helpful, it shows what's working..

Easier to get this information from the VECTACTIVE field in SCB->ICSR.

LSB of IABR0 corresponds to "NVIC position" 0 which is WWDG1 here. Goes up from there, 32 per register.

13 of them don't have "NVIC position" values because they're system interrupts and not reported anywhere in IABR.

If you feel a post has answered your question, please click "Accept as Solution".

That information helps. But its easier to add 16 to the NVIC postion?

The count without "NIVC position" is actually 16 like you said before. There is one row that includes more than one address.

 

VECTACTIVE does not correspond with the IABR.

What i get, is position 27 and 44 in IABR and 60 in VECTACTIVE?

It would make sense, if 16 is beeing subtracted from 60. Quite confusing. Why isnt there some better documentation? Or is there any?

 

I said 13 to make it simpler. You are correct that there are 16.

If bit 0 in IABR is set, that corresponds to VECTACTIVE=16.

If bit 27 is set, that is VECTACTIVE=43.

If bit 44 is set, that is VECTACTIVE=60.

> It would make sense, if 16 is beeing subtracted from 60. Quite confusing. Why isnt there some better documentation? Or is there any?

There is documentation, but it's not great and is hard to find. As for why, perhaps ask ARM.

If you feel a post has answered your question, please click "Accept as Solution".

Thank you for you help.

You said 16 at first, then changed to 13, which is confusing. (You may want to change this for future readers).

Now it makes all sense.

But STM as a licensee should contact ARM in this regard. ARM would never listen to a individual, that even hasnt got any professional electronics or electrics background.