After brief review of AN4760, I get an impression that QuadSPI was specificaly designed to interface Flash memory IC.
ADC has absolutely different requirements in respect to timing on CS line, clock - 32 SCLK clocks with 16 data bits.
See pictures:
After brief review of AN4760, I get an impression that QuadSPI was specificaly designed to interface Flash memory IC.
ADC has absolutely different requirements in respect to timing on CS line, clock - 32 SCLK clocks with 16 data bits.
See pictures:
