Multiple SDRAM chips arrangements on 144 pin TQFP STM32F7 series clarification

[Tokarev.Konstantin]

Hello everybody!

I am looking into possibilities of having 256 megabytes of SDRAM memory on a 144 pin STM32F7 chip. As I understand the 144 pin chips only have 16 bits data bus available for the SDRAM interface, so I was looking into using two, 8 bit data bus 512megabit chips (because they are readily available), sharing everything but the databus pins, which would go separate to make up the 16 bits, and give me a total of 128 megabytes. Now, I was wondering about the SDRAM1 and SDRAM2 interfaces which are available on these STM32F7 chips.. one uses SDCKE0+SDNE0 clock and chip enable pins and the other SDCKE1+SDNE1 pins. I am trying to understand how this works, given that both SDRAM1 and SDRAM2 seem to be sharing all of the other pins. Would it be possible for me to connect a second pair of SDRAM chips to all the same interface pins used by the first pair, but using these other clock and chip enable pins, in a sort of a "multiplexed" way where both pairs of chips can be accessed? Or am I really just limited by the 16 bit maximum data bus width of the 144 pin chips series, and a maximum of 2 physical SDRAM chips? If so, what is the purpose of the 2 separate SDRAM1 and SDRAM2 interfaces that can be enabled simultaneously (saying this based on what STM32CUBE software shows)?

Basically, I am looking forward to having 256 megabytes of ram to store and playback a high quality stereo WAV file. If there are better ways than using SDRAM, ideas are welcome! Need to be a type of RAM that could support unlimited read/write cycles.

Thank you in advance for any advice!

Best regards,

Konstantin

[Tesla DeLorean]

Aren't there 2 SDRAM banks, basically 0xC0000000 and 0xD0000000 at 256MB each.

You could likely make a more exotic arrangement behind a CPLD / FPGA, and have your own banking scheme.

[Tokarev.Konstantin]

Thank you for your answer!

This is what I was wondering about, those 2 banks.. If I were to use the both at the same time, I suppose the SDRAM chips would have to be connected in parallel sharing the data and address lines, plus control pins, but using separate Chip Select and Clock pins?, correct me if I am wrong please.

I drew this "simplified" scheme of how I figure it should be connected. The arrangement is, four 512Mbit, 8 bit data bus SDRAM chips, which would be connected to both SDRAM banks configured for 16 bit data bus. Could I kindly ask you to check this diagram and see if my theory is right? Besides the general structure of the connections.. specially wondering about the connection of the "DQM" pin of the memory chips, should they be connected to the FMC_NBL0 and FMC_NBL1 pins, each pair of chips to its own pin?

Here is the diagram:

https://imgur.com/a/psdYU3B

FPGA would be nice but thats a bit beyond the scope of this project.. although its a topic i would love to dive into one fine day.

Thanks for advice once again!

Best regards,

Konstantin