Multi-Channel I2S Hardware Design on an STM32F413/423

[EDeYo.1]

The microcontroller will be doing little else besides some very light processing on the audio data. The I2S source has a single MCK, SCK, WS, and 4 stereo outputs (3 of which will be used), and the I2S source can ONLY function as a master device, leaving me to use the STM32 as a slave. I see that there is a CKIN pin for I2S labelled as I2S2_CKIN. Looking at the clock routing diagram in the datasheet, it looks like that can be routed to the I2SPLL before being distributed back to I2S peripherals (1,4,5 as well as 2,3). I'll likely provide that as an option in hardware so that I can choose between the external I2S clock input or using the HSI/HSE clock. My question lies in the fact that all of the I2S data channels share WS and SCLK signals. Do I need to buffer/split these signals to go to each peripheral instance, or is there a way that they can be synced between peripherals in firmware? I don't see the mechanism to do it right off the bat in firmware, but looking for someone who may have run into the same issue!

Thanks!

[Imen.D]

Hi,

Regarding the post SAI Clock Generator in Slave mode, I've heard back from the expert team:

When the SAI is working in slave mode, the SAI clock generator is no longer needed, but the kernel clock (SAI_CK) must still be present.

It is used to perform the clock domain crossing from bits in the APB clock domain to the serial clock domain (such as SAIEN bit).

In slave mode, there is no specific constraint in term of accuracy for the kernel clock, the speed is not critical as well.

The slower the kernel clock is, the more time it will take to transfer bit values in the serial clock domain.

This implementation makes the SAI configuration independent from the serial interface clock, which may not be present.

Hope that I've answered your question :).

All questions or feedback are welcome.

Imen

[waclawek.jan]

Hi Imen,

Thanks for the answer.

Jan

@Imen DAHMEN​