Okay. Really strange. Especially the case that with OSR set it works.
Maybe you're not turning off the peripheral before changing the clock settings?
Do you use CubeMX / HAL for setup?
If yes, try using direct register settings, that gives you better control anyway.
It's not that many settings for I2S.
For inspiration, here's my SAI1 init, but for a H723/H735 (slightly different registers), with SAI1A as RX master and SAI1B as synced RX slave:
void SAI1_Init(void)
{
/* ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ */
/* SAI 1 A, SYNC master, I2S INput --> ADC */
/* creates SCLK, LRCK */
/* DMA stuff simpler with SAI handle */
hSai_1_A.Instance = SAI1_Block_A;
/* Initialize the SAI state for DMA */
hSai_1_A.State = HAL_SAI_STATE_READY;
/* GPIO and DMA init */
SaiDmaGpio_Init(&hSai_1_A);
/* SAI register init */
/* CR2 - unused: compander, FIFO, tristate */
hSai_1_A.Instance->CR2 = 0;
/* CR1: most important settings here
* DMA and SAI enable are set when started
* SAI_xCR1_MCKEN = 0 MCLK is OFF, we use extra I2S for MCLK cause we need OSR 128 at 200 kHz
* SAI_xCR1_OSR = 0 x256 oversampling
* SAI_xCR1_NODIV = 0 use SAI_xCR1_MCKDIV for sampling rate settings
* SAI_xCR1_SYNCEN = 00 async mode, SAI_1_A is master
* SAI_xCR1_CKSTR = 1 I2S: sample on SCK rising
* SAI_xCR1_LSBFIRST = 0 MSB first
* SAI_xCR1_DS = 111 32 bit data size
* SAI_xCR1_PRTCFG = 00 free protocol
* SAI_xCR1_MODE = 01 master receiver
*/
hSai_1_A.Instance->CR1 = ( SAI_CR1_MCKDIV_SR_200K | SAI_xCR1_CKSTR |
SAI_CR1_DS_XBIT | SAI_CR1_MODE_MSTR_RCV );
/* FRCR: frame configuration -> FS = LRCK */
hSai_1_A.Instance->FRCR = 0;
hSai_1_A.Instance->FRCR |= SAI_xFRCR_FSPOL; /* FS active high */
hSai_1_A.Instance->FRCR |= SAI_xFRCR_FSDEF; /* FS is start of frame AND channel side ID -> LeftRightCK */
hSai_1_A.Instance->FRCR |= SAI_FRCR_FSALL_32; /* frame length active in bit clocks = 32 (-1) */
hSai_1_A.Instance->FRCR |= SAI_FRCR_FRL_64; /* frame length in bit clocks = 64 (-1) */
/* SLOTR: slot configuration -> SCLK / LRCK */
hSai_1_A.Instance->SLOTR = 0;
hSai_1_A.Instance->SLOTR |= SAI_SLOTR_SLOTEN_ALL; /* all slots active */
hSai_1_A.Instance->SLOTR |= SAI_SLOTR_NBSLOT_2; /* number of slots in frame = 2 (-1) */
hSai_1_A.Instance->SLOTR |= SAI_SLOTR_SLOTSZ_32; /* slot size = bits per channel */
/* ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ */
/* SAI 1 B, sync slave, I2S INput --> ADC */
/* SCLK, LRCK from master SAI_1_A */
/* DMA stuff simpler with SAI handle */
hSai_1_B.Instance = SAI1_Block_B;
/* Initialize the SAI state */
hSai_1_B.State = HAL_SAI_STATE_READY;
/* GPIO and DMA init */
SaiDmaGpio_Init(&hSai_1_B);
/* SAI register init */
/* CR2 - unused: compander, FIFO, tristate */
hSai_1_B.Instance->CR2 = 0;
/* CR1: most important settings here
* DMA and SAI enable are set when started
* SAI_xCR1_OSR = 0 x256 oversampling
* SAI_xCR1_NODIV = 0 use SAI_xCR1_MCKDIV for sampling rate settings
* SAI_xCR1_SYNCEN = 01 sync mode same block, SAI_1_A is master
* SAI_xCR1_CKSTR = 1 I2S: sample on SCK rising
* SAI_xCR1_LSBFIRST = 0 MSB first
* SAI_xCR1_DS = 111 32 bit data size
* SAI_xCR1_PRTCFG = 00 free protocol
* SAI_xCR1_MODE = 11 slave receiver
*/
hSai_1_B.Instance->CR1 = ( SAI_CR1_SYNCEN_SYNC_INT | SAI_xCR1_CKSTR |
SAI_CR1_DS_XBIT | SAI_CR1_MODE_SLAVE_RCV );
/* FRCR: frame configuration -> FS = LRCK */
hSai_1_B.Instance->FRCR = hSai_1_A.Instance->FRCR; /* copy from sync master */
/* SLOTR: slot configuration -> SCLK / LRCK */
hSai_1_B.Instance->SLOTR = hSai_1_A.Instance->SLOTR; /* copy from sync master */
/* ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ */
/* GCR:
* - for both blocks of SAI
* - SYNC configuration to other SAIs / blocks
* - SAI1:
* - output: A is master
* - input: none
*/
SAI1->GCR = SAI_GCR_SYNCOUT_A;
/* calculate audio sampling rate */
u32SaiSamplingRate = SaiGetSamplingRate(&hSai_1_A);
}
