2023-02-27 05:22 AM
Hello together,
when inspecting the behaviour of the HRTimer regarding the compare output, I found that with Clk multiplier 32, there is a non-linearity in the compare timing (stepwidth) of about +150 ps (330 ps step instead of 180 ps between adjacent compare values). This seems directly to correlate with the depth of the delay line, as I can see this step equally distributed each 32 steps.
Is this known or is there a way to avoid this behaviour and get a more linear behaviour?
My test setup is:
STM32G474, HRTim1
Channel B: 1 MHz pulses, continious
Channel C: single shot, resettable, triggered by Chan B, variable compare value. Set on compare, reset on period.
I checked the delay of the output C regarding to B. Basically I get quite good results with a standard deviation of appr. 30 ps but I wonder of this non-linear step. The step e.g. happens when changing the compare value from 183 to 184 (or 215 to 216).
Br,
Pascal
2023-12-29 07:39 PM
I have similar concerns. Any update on this?
2023-12-30 08:34 AM
Does this function make any difference:
if (HAL_HRTIM_DLLCalibrationStart(&hhrtim1, HRTIM_CALIBRATIONRATE_3) != HAL_OK) ?
FYI, HAL driver internal info:
#define HRTIM_SINGLE_CALIBRATION 0xFFFFFFFFU /*!< Non periodic DLL calibration */
#define HRTIM_CALIBRATIONRATE_0 0x00000000U /*!< Periodic DLL calibration: T = 1048576U * tHRTIM (6.168 ms) */
#define HRTIM_CALIBRATIONRATE_1 (HRTIM_DLLCR_CALRTE_0) /*!< Periodic DLL calibration: T = 131072U * tHRTIM (0.771 ms) */
#define HRTIM_CALIBRATIONRATE_2 (HRTIM_DLLCR_CALRTE_1) /*!< Periodic DLL calibration: T = 16384U * tHRTIM (0.096 ms) */
#define HRTIM_CALIBRATIONRATE_3 (HRTIM_DLLCR_CALRTE_1 | HRTIM_DLLCR_CALRTE_0) /*!< Periodic DLL calibration: T = 2048U * tHRTIM (0.012 ms) */