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Arbitrary pwm signal generation of high resoultion timers in converter mode transistion.

Naser_hassanpour
Associate

Hi dear friends

I am controlling a current source DC-DC converter using a stm32g474 microcontroller. I am using all 6 HRTIMs to generate 12 PWM signals for my 12 switches. My converter has different operation modes and in each one, these 12 timers have their compare value register (CMP) values and different phase shifts relative to each other. The problem is that when transitioning from one mode to the next mode, these compare values and phase shifts must change and among this mode change, the HRTIM outputs give arbitrary signals for 3-4 switching cycles. This means that the switches do not receive correct modulation signals and transistors burn. How I can control the HRTIM outputs exactly cycle by cycle when a flag for mode transition becomes high and gives the order for mode change? 

I must mention that the converter is a current source converter and I cannot switch off the timers for some cycles to reconfigure them and turn them on. It will burn all the transistors. I need to change the mode smoothly when the converter continues its operation

1 ACCEPTED SOLUTION

Accepted Solutions
Pierre_Paris
ST Employee

Hello @Naser_hassanpour,

Here some remark question to support you :

  • How are you currently changing mode ? 
  • What do you mean with smoothly ? In which way ?
  • Are you aware of the Burst DMA transfers on HRTIM ? This allows to update data registers and reprogram dynamically timing units. You can define, thanks to UPDGAT[3:0], how the update occurs relatively to the burst DMA transaction and the external update request on update enable inputs. You may be interested in one of the use case when preload (PREEN bit set) is enabled : "2. the update is done when the DMA burst transfer is completed (UPDGAT[3:0] = 0000 in HRTIM_TIMxCR and BRSTDMA[1:0] = 01 in HRTIM_MCR). This mode guarantees that all new register values are transferred simultaneously. This is done independently from the counter value and can be combined with regular update events, if necessary (for instance, an update on a counter reset when TxRSTU is set)."(page 943 of RM0440). You can read more in chapter 27.3.23 of this Reference Manual. 

Best Regards,

Pierre

To give better visibility on the answered topics, please click on Accept as Solution on the reply which solved your issue or answered your question.

View solution in original post

2 REPLIES 2
Pierre_Paris
ST Employee

Hello @Naser_hassanpour,

Here some remark question to support you :

  • How are you currently changing mode ? 
  • What do you mean with smoothly ? In which way ?
  • Are you aware of the Burst DMA transfers on HRTIM ? This allows to update data registers and reprogram dynamically timing units. You can define, thanks to UPDGAT[3:0], how the update occurs relatively to the burst DMA transaction and the external update request on update enable inputs. You may be interested in one of the use case when preload (PREEN bit set) is enabled : "2. the update is done when the DMA burst transfer is completed (UPDGAT[3:0] = 0000 in HRTIM_TIMxCR and BRSTDMA[1:0] = 01 in HRTIM_MCR). This mode guarantees that all new register values are transferred simultaneously. This is done independently from the counter value and can be combined with regular update events, if necessary (for instance, an update on a counter reset when TxRSTU is set)."(page 943 of RM0440). You can read more in chapter 27.3.23 of this Reference Manual. 

Best Regards,

Pierre

To give better visibility on the answered topics, please click on Accept as Solution on the reply which solved your issue or answered your question.

Naser_hassanpour
Associate

Thank you for your answer. I am currently using HRTIMs A, B, C, E, and F. The master timer synchronizes all of them, and the master timer update triggers their register update. Moreover, the time C is reset on the master timer period event. Timers A, B, E, and F reset on master timer's compare values 1, 2, 3, and 4 events respectively. By doing so, I want to implement a phase shift modulation with different master timer compare values. When I am transferring from one mode to the next mode, I update both timers' compare values (A, B, C, E, F) and the order of their relative phase shift which means changing master timer compare values 1-4. It means that two simultaneous updates happen in this process. Firstly, the duty cycle values of timer outputs by their CMPs and second their reset point by the master timer CMPs. For all the timers, the preload register is enabled and I disable their update when I want to update compare value registers and after all new values calculation, again I enable the timers update. By the word smooth I mean that I expect the outputs to instantly change to the new modulation at the same time without losing any cycle. However, in reality, the timers generate a very random pwm for two cycles and then they generate the correct output. I did not use burst DMA for updating the timers. Here I attach an image taken from an oscilloscope that shows the timer outputs. As you see, outputs 3 and 4 are changing from off to PWM mode, but their first cycle is a PWM with a random duty cycle. The same problem happens for 5 and 6. They are changing from turn-on to PWM mode but again they turn off at a very random point and their first two cycles are incorrect. These random switchings create a short circuit and open circuit for a different part of our converter and burn the switches.

I will try to study and apply your mentioned solution but could you please provide me an example or project to which I can refer? Thank you so much.