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Issues with ADC Calibration STM32L031F4

RArch
Associate II

I'm working with an STM32L031F4 and I'm trying to calibrate the ADC to no avail. I'm wondering what it is that I'm missing here.

With the code snippet below, I never get out of the while loop and the CALFACT stays at 0 (if I understand correctly, CALFACT should be updated with the calibration results upon completion).

	RCC->APB2ENR |= RCC_APB2ENR_ADCEN;
	ADC->CCR |=	 ADC_CCR_LFMEN;	//set Low Frequency bit since I'm running <3.5M
	ADC1->CFGR2 |= (1 << 31); //set up clock for a /4 prescaler
	ADC1->CR |= ADC_CR_ADDIS; //ensure that ADC is off
	ADC1->CR |= ADC_CR_ADCAL; //start calibration
	while ((ADC1->ISR & ADC_ISR_EOCAL) == 0){}
	ADC1->ISR |= ADC_ISR_EOCAL;

The ADC clock is enabled prior to attempting to calibrate...Clock is the MSI at 2.09M with a /4 prescaler set by CFGR2..

I'm not overly concerned about this as I'm getting good data out of the ADC without calibration, but I'd like to understand why this isn't working.

It looks like a HAL-based project utilizing the ADC doesn't do this calibration either...This is my first HAL-less STM32 project and I might be missing something obvious but if anybody could offer advise I'd appreciate it.

1 ACCEPTED SOLUTION

Accepted Solutions

Don't set ADDIS unless ADEN was set previously.

In other words, remove this line:

ADC1->CR |= ADC_CR_ADDIS; //ensure that ADC is off

and try again.

JW

View solution in original post

4 REPLIES 4

Read back and check/post the ADC register's content.

JW

0690X00000AQSi8QAH.pngThanks for the reply. I set bit 31 of the CR register (in line 4 of the code snippet above) but it just seems to stay in that state until I reset.

Don't set ADDIS unless ADEN was set previously.

In other words, remove this line:

ADC1->CR |= ADC_CR_ADDIS; //ensure that ADC is off

and try again.

JW

Thank you JW. The calibration is working now...thanks for taking the time to offer some great advice!

Cheers,

Roger