I have an STM32-L4P5DK connected to an external ADC, with SPI2 configured to read ADC samples on every falling edge of the DRDY signal. The DMA1 configuration is as follows:
DMA1 CHANNEL1: DMA_GENERATOR0
DMA1 CHANNEL2: SPI2_TX
DMA1 CHANNEL3: SPI2_RX
The DRDY pin is connected to EXTI1. On each falling edge of DRDY, DMA_GENERATOR0 generates a request to set the Chip Select pin low. The SPI_TX DMA request is synchronized with the rising edge of DRDY, so SPI_TX transmits dummy bytes to read the ADC data via SPI_RX DMA request, which is also synchronized with the EXTI1 rising edge. Once the SPI transmission is complete, I set the Chip Select pin high in the `HAL_SPI_TxCpltCallback` function.
The problem is that the Chip Select pin goes high before the SPI transmission completes. However, if I add a delay using a while() loop, the Chip Select timing shifts correctly.
Why is this happening, and how can I ensure that the Chip Select pin goes high only after the SPI transmission is completely finished?
void HAL_SPI_TxCpltCallback(SPI_HandleTypeDef *hspi)
{
HAL_GPIO_WritePin(CS_GPIO_Port, CS_Pin, 1); //callback function without delay
}for the above function , I get the below output.
fig 1:
void HAL_SPI_TxCpltCallback(SPI_HandleTypeDef *hspi)
{
uint8_t i =21;
while(--i) // added delay to shift CS pin HIGH state
{
__NOP();
}
HAL_GPIO_WritePin(CS_GPIO_Port, CS_Pin, 1);
}for the above function , I get the below output.
fig2:
Scope output:
>> yellow - DRDY , green - CS , red - SCK , blue - MOSI
> Why is this happening
The DMA transfer completes when the last byte of data is sent to the peripheral. Since the peripheral has a FIFO, this happens before some bytes before the data is actually sent out. (Even without a FIFO, it would happen before the last byte is sent.)
> and how can I ensure that the Chip Select pin goes high only after the SPI transmission is completely finished?
Poll the SPI BSY bit and wait for it to be 0 before de-asserting CS.
This is actually covered in the RM:
