Issue with AD conversions: limited resolution using STM32g484?

[ARein.2]

We are using two of the ADCs (ADC1 and ADC2) on the STM32g484 and have encountered massive resolution problems.

The final goal is to convert two values per ADC and to operate the two ADC converters in coupled mode in combination with the DMA.

Both with single conversions of the single ADCs, using the coupled mode with and without DMA and calibration and no calibration of the ADCs offsets occur (see measurement).

In this forum post (Issue with AD conversions, 10th September 2020) we have seen that the resolution of some controllers is only 6 bits.

Converting a constant voltage shows that the 4 bits (LSB) flip randomly.

Can the resolution limited to 6 bits be confirmed?

Is this only true for a specific lot or for all controllers?

[waclawek.jan]

> In this forum post (Issue with AD conversions, 10th September 2020) we have seen that the resolution of some controllers is only 6 bits.

You are talking about this? https://community.st.com/s/question/0D53W00000HO2b7SAD/issue-with-ad-conversions

The problem there was conclusively identified by the OP+ST as ADC clock set to 170MHz while maximum allowed ADC clock is 60MHz.

> Converting a constant voltage shows that the 4 bits (LSB) flip randomly.

I see data you've provided to fluctuate between 999 and 1002 i.e. 4 bins, equivalent to 2 LSB error.

ADC data stability is dependent on many factors, but the usual culprits are stability of VDDA and, most importantly, VREF+; this depends often on the particular routing and decoupling of these signals and VSS/VSSA.

Read AN5346.

JW