Is there any conflict in text and legend about PLL source in STM3232F303VET?

[Jinlong Shen]

Details: In the reference manual for stm32f303vet (rev 8) Figure 14, the PLL source is HSE by default if HSE is selected as source. In Page 140 bit Bits16:15, it says the default is HSE/2 and so on.

This point is important since different stm32f303 variants have different diagram about PLL source.

[Jinlong Shen]

@Jeanne Joly_O​ Could you take a look at my question?

[waclawek.jan]

> Figure 14, the PLL source is HSE by default if HSE is selected as source

No, it's HSE divided by PREDIV.

 

> In Page 140 bit Bits16:15, it says the default is HSE/2 and so on.

No, default is HSI/2.

JW

[Jinlong Shen]

Sorry, for my typo. I mean that we select HSE as the PLL clock source on STM32F303VET.

We use PLLSRC bit 16:bit15 = 0b10. PLL_MUL = 9. RCC_CFGR2_PREDIV is not changed (i.e. it has the reset value). I do not understand PREVID1. But the entry to PLL is then Frequency_HSE, right?

[waclawek.jan · Accepted solution]

PREDIV1 is probably PREDIV (maybe this is copy/paste from some other STM32 manual where there are several numbered prescalers in RCC).

After reset PREDIV is set to 1, so with your setting you should see at the output of PLL frequency which is HSE * 9.

Is your experience different?

JW

[Jinlong Shen]

Thanks. It should be HSE *9 in our case. Please close this thread.