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Is it possible to synchronise the four I2S FS outputs in master mode on an H7B0 device ?

MikeDB
Lead

I need to have the four I2S inputs on the H7B0 device synchronised so that they all sample the ADCs at exactly the same time. One method is to run the I2S modules in slave mode and input an external FS and CK to all four I2S and to the ADCs, but it would be easier if the device can generate the four FS signals in sync itself. I originally thought put one I2S module in master mode and rest in slave mode and feed FS output from one into other three, but now not sure this will work as there could be a one-clock difference between master and slave I2Ses.

8 REPLIES 8

> there could be a one-clock difference between master and slave I2Ses.

The one-clock delay of data to WS/LRCK/FS/framing-clock in I2S is there exactly to prevent that.

JW

AScha.3
Principal III

one master , others slave receiver : will be ok.

just look at SDI/SDO swap in slave mode vs master mode.

@Community member​ - "The one-clock delay of data " - i never understood, because clocking in or out data , slave or master, needs no extra delays. so why Philips did this? because need some obvious difference to "normal" (= no curious bit delays) ?

here the standard I2S timing:

0693W00000UoAcUQAV.pngall bits in frame :

0693W00000UoAdNQAV.png 

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> "The one-clock delay of data " - i never understood, because clocking in or out data , slave or master, needs no extra delays.

It allows the slave transmitter to perform a clean initialization sequence:

  • wait until WS right-to-left (downgoing) edge
  • now you have roughly one bit time to perform whatever you need to do internally to load the first word into the shift register
  • wait for the CK sampling (upgoing) edge
  • enable CK to shift register, so that upon next CK shift (downgoing) edge the first data bit is shifted out

With the MSB timing, you would need to have the first data ready beforehand; and also output its first bit upon WS transition rather than upon CK transition, which means the first data bit may have different duration due to potential clock skews and internal logic delays (the WS logic is "heavier" than the CK logic). The difference is entirely negligible nowadays, but (cheap commercial) logic was way slower back then.

JW

MikeDB
Lead

> just look at SDI/SDO swap in slave mode vs master mode.

Hadn't noticed that thanks. But datasheet must be wrong in one place or another

55.9.2 :

• SDO: Serial Data Output (mapped on the MOSI pin) to transmit the audio samples in

master, and to receive the audio sample in slave. Refer to Section : Serial Data Line

swapping on page 2129.

• SDI: Serial Data Input (mapped on the MISO pin) to receive the audio samples in

master, and to transmit the audio sample in slave. Refer to Section : Serial Data Line

swapping on page 2129.

Goto page 2129 and the information isn't the same :

Serial Data Line swapping

The SPI/I2S offers the possibility to swap the function of SDI and SDO lines thanks to

IOSWP bit located into SPI configuration register 2 (SPI_CFG2). Table 406 gives details on

this feature.

Table 406. Serial data line swapping

This show the input for Master & slave RX to be on SDIN unless you set IOSWP = 1. But says IOSWP = 0 is default.

Any idea which is correct ?

AScha.3
Principal III

i had this problem and cost me some hours... on STM32H743 :

when switch master -> slave transmitter , SDO becomes SDI !

so need swap ( set =1) to get data on same pin as before in master mode.

see here , same pin (MOSI) is connected to in or out , depending on master/slave setting !

0693W00000UoCJPQA3.pngi tell my problem here:

 https://community.st.com/s/feed/0D53W00001oJqe3SAC

If you feel a post has answered your question, please click "Accept as Solution".

Good how the ST person references a table that is wrong !

But I've only ever used the H7s in master mode before as well.

Piranha
Chief II

Doesn't anyone see the elephant in the room? Why are you not using the SAI? Your device has two SAI peripherals, which can provide 4 I2S lines all synchronized. Configure one SAI block as a master and 3 others as a synchronous slaves. Enable the slaves first and the master as the last one. Disable the master as the first one and the slaves after that.

And SAI peripheral is anyway the recommended choice for audio protocols instead of SPI/I2S peripheral.

MikeDB
Lead

Because I need SAI#1 to transmit the eight channels of processed data out into a multichannel mixing ring (4 channels per block).

So SAI#2 will be the master on the ADC side and the three I2S interfaces slave to it.

I agree it would be nice if they just dropped the I2S interfaces and always offered SAIs, but they haven't so far.