Is it possible to configure TIM1, 2, 3 and 17 as both master and slave?

AB · ‎2018-10-19

Purpose is to generate 4 mutually phase shifted PWMs. Regular master/slave mode will require 8 timers in that case (right?). So thought of using the following, if possible:

TIM1 = master to TIM2, TIM2 = slave of TIM1 and master to TIM3, TIM3 = slave of TIM2 and master to TIM17, TIM17 = slave of TIM3 (Will have to make sure there is no interlock which prevents TIMx and TIMy to be in master slave mode). Device planning to use is: STM32F334xxx.

HRTIMs already used up.

Singh.Harjit · ‎2018-10-19

You can have one timer be the master and the others be the slaves.

Looking at the block diagram for timer 17 in reference manual (Figure 213), timer 17 cannot be a slave to any other timers.

I'll walk you through how to synchronize timer 1, 2 and 3 and if you can redo your timer assignments, you might be able to find a solution.

The TIMx_CR2 register's MMS field selects which event on a timer generates an event on that timer TRGO (or TRGO2 if it has one) signal.

The TIMx_SMCR register's TS field selects the trigger event source that timer will listen to.

The TIMx_SMCR register's SMS field select what that timer does when it gets the trigger / event.

Since we want timer 1 to be the master, configure its TRGO (in TIM1_CR2) to generate a TRGO when timer 1 is enabled (MMS[2:0] = 001

NOTE: The reference manual has an error on page 445 and it says: Bits 6:4 MMS[1:0]. Clearly it should say Bits 6:4 MMS[2:0]

Then, for timer 2 and 3, configure TIM2_SMCR and TIM3_SMCR, SMS[3:0] to 0110 to enable them when they receive an active edge on TRGI.

To select which signal to use for TRGI, we want timer 1 which using table 73 is ITR0 which means set TS[2:0] = 000

If for example, you could use timer 15 instead of timer 17, you will notice that it only has internal trigger connections to timer 2, 4, 16 OC1 and 17 OC2 (table 76). So, you cannot have timer 1 trigger timer 15!

What would could do is make timer 1, 3 and 15 slaves and timer 2 the master. Now, when you enable timer 2, the others will be simultaneously enabled.

View solution in original post

T J · ‎2018-10-19

can you draw your output waveform requirement ?

AB · ‎2018-10-19

Here is a quick picture. Its kind of in burst mode for ~40 ms and remains high for ~40ms.

AB · ‎2018-10-19

T J · ‎2018-10-19

it is stepper motor ?

A and B are inverted, did you see the complementary outputs on Tim1 ?

A would be CH1, B would be CH1N, C would be CH2, D CH2N

AB · ‎2018-10-19

No its a power converter. A and B are complementary during the burst mode but then they both become high, I cant use CH1 and CH1N. They all have to be separate phase shift as far as I can understand.

T J · ‎2018-10-19

you would have to set an interrupt to switch the functionality, not great solution, but workable

can you use external gates ? to save all the urgency

try a LS139 nice chip. ( its dual 2:4, so you have a spare)

connect 1E to Gnd // to enable outputs

connect the (TimerCh1PWM) to 1A0 // switching from channel A to B

connect another output to 1A1 (maybe another PWM to switch channels from AB to CD)

when 1A1 is High, CD is operational.

when 1A1 is Low AB is running.

AB · ‎2018-10-19

Don't wanna use external chip. I am moving from FPGA to STM just because it comes in a package. How about the solution I proposed in the question, does that seem doable? I saw a doc online which says that a timer can be simultaneously in master and slave mode, but thats about it. Need help/doc on this. Or need someone to tell me that's not going to work for the device I've chosen.

T J · ‎2018-10-19

Guys ? what is the real answer ?

you could do it with timer interrupts, you would have to run a state machine,(easy enough) and toggle the appropriate IO pin.. make sure its the highest priority, its not a great solution.

otherwise again under interrupt, after the PWM period, you would switch sides... from AB to CD by shutting down 2 channles and bringing up the other two. also not great due to interrupt latency.

much easier with 2 PWMs and 1x LS139 and no interrupts...

IMHO :)

note to all:

I remind myself continually, "Be careful what you wish for, "

you can spend a lot of time implementing the wrong approach, just to dump it after weeks of failures.

AB · ‎2018-10-19

well, I need deadtime on the PWMs as well (whenever needed during operation). I dont think complement channels are suitable here. Also, will shutting down channels work? I need constant "high" on them. I was thinking more like 100% duty ratio for the high period.