Interfacing STM32 with External 512kx16 SRAM, 8bit data only accessible per one address of RAM

[vishal patel]

Posted on February 25, 2017 at 11:44

Hi,I have STM32F4 interfaced with the external SRAM sized 512kx16 array. Now what I believe is (Pls correct me if i am wrong), Pointing to Every incremental Address should give me 16bit data. because SRAM is interfaced with 16bit wide data bus (non multiplexed)

For Example: 0x64000000 is the base address of my external SRAM. And I want to write hello, to this RAM, then It should happen like...

on 0x64000000 location, data should be written, 'H' 'E' &

on 0x64000001 location, data should be written, 'L' 'L' &

on 0x64000002 location, data should be written, 'O' 0xff .

And the same is should be getting in read back. But What actually occurs is

on 0x64000000 location, data iswritten, 'H' 'E' &

on 0x64000001 location, data is written, 'E' 'L' &

on 0x64000002 location, data

is

written, 'L' 'L' &

on 0x64000003 location, data is written, 'L' 'O' &

on 0x64000004 location, data is written, 'O' 0xff .

So If I want to get the write data, I will have to read back 16 bit data from location

0x64000000,0x64000002, and 0x64000

Can Anyone Has the experience of interfacing 512kx16bit array SRAM ? and facing the similar issues ??

#external-ram #sram #stm32 #dma #fsmc Note: this post was migrated and contained many threaded conversations, some content may be missing.

[vishal patel]

Posted on February 28, 2017 at 06:16

Yes, It access two bytes at once.But, It read-write 1 byte per 1 address location only. Problem is not regarding accessing capacity, sure it is 16bit and I am able to evaluate in my system. Problem is about utilizing memory area, by given number of address lines. 

Let me try to make more clear.

I have interfaced the SRAM as per the schematic in attachment.

As you can see, I have used A0-A18 address lines, which is 19, as per simple math rule, total addressable area is 0 to 524287(2^19).

Now as per the data sheet, the SRAM we use - AS6C8016, has the 1MegaByte capacity. But with 19 address line I am able to access only 512KByte memory.

Accessing each address combinations(0x00000000 - 0x0007FFFF) on A0-A18 gives me 1 byte data only, so At present, total accessible memory with this architecture is 512Kbyte.

[T J · Accepted solution]

Posted on February 28, 2017 at 06:31

yes, I can see your diagram looks good.

and the problem is that pins A0-A18 are actually shifted inside the processor to A1-A19 (suggested by Clive)

So you can be sure your addressing is now 20 bits wide,

So the result is that your address range should be 0- 0xFFFFF

please try that,

[vishal patel]

Posted on February 28, 2017 at 06:36

Thank you very much.

I have already interfaced SRAM with STM32F4 as per the application guide. And It works fine as long as I don't care to use whole area of RAM. This configuration gives me access to only 512Kbyte. I want to understand where I am making mistake, I have also checked in the manual write operation that I can not access the address above 512k, It will just give me 0xFF, If I try to do so.   

[vishal patel]

Posted on February 28, 2017 at 06:39

Ok. Understood I guess.  Let me try and Will give you feedback. Thanks all for your time. 

[world04]

Posted on February 28, 2017 at 09:00

I assume the issue is solved now. The datasheet i pointed to, explain how the signaling must be done. It's not explain how the MPU handle the byte control pins. I am sure that this are not just placed into the A0 line.

If i have a board that requires external sram, i will check up how the f4 handles this lines. 

[T J]

Posted on March 11, 2017 at 10:41

Did it work, can you mark the answers as correct ?